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v4: Updated the wait dependancy bars based on tex component masks. This patch adds proper delays to maxwell exa shaders. Tested with rendercheck -f a8r8g8b8. I am still wondering whether the rd's are required. We could still wait on the write bars instead. eg. see "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.f...

...3 insertions(+), 93 deletions(-) diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp index ce78036..101b67f 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t...

...3 insertions(+), 93 deletions(-) diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp index ce78036..1c4a4f1 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t...

Hi, On Wed, Jun 28, 2017 at 12:53 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > BTW, you can drop those explicit "depbar" ops. I think they're only > needed when you're doing something weird with barriers. Blob doesn't > use them (anymore) > Gotcha. Should I remove them in the same patch or a different one? It seems like the depbar remo...

On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Nice work! > > See my comments below, and double-check if some of them can be applied to > the shaders I didn't review yet. > > I recommend you to test your work because if one sched code is wrong, you > are likely going to kill your card and reboot your box. :-) &gt...

...8 insertions(+), 88 deletions(-) diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp index 220d7e5..7797ef4 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,22 +25,22 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 wt 0x3) (st 0xf wr 0x0 wt 0x1) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8...

Do you still have some glitches or does it work correctly now? Did you also remove the spurious wait dep bars between v3 and v4? On 06/27/2017 05:16 PM, Aaryaman Vasishta wrote: > v4: Updated the wait dependancy bars based on tex component masks. > > This patch adds proper delays to maxwell exa shaders. Tested with > rendercheck -f a8r8g8b8. > > I am still wondering whether the rd's are required. We could > still wait on the write bars instea...

BTW, you can drop those explicit "depbar" ops. I think they're only needed when you're doing something weird with barriers. Blob doesn't use them (anymore) On Tue, Jun 27, 2017 at 11:16 AM, Aaryaman Vasishta <jem456.vasishta at gmail.com> wrote: > v4: Updated the wait dependancy bars based on tex component masks. > > This patch adds proper delays to maxwell exa shaders. Tested with > rendercheck -f a8r8g8b8. > > I am still wondering whether the rd's are required. We could > still wait on the write bars instead....

...3 insertions(+), 93 deletions(-) diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp index ce78036..1c4a4f1 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t...

See the 'wt' on the first fmul in exacanv110.fp, exacmnv110.fp and exasanv110.fp. Any ideas on what could be causing the first fmul to require $r0 and/or $r1? Cheers, Aaryaman On Sat, Jun 10, 2017 at 4:10 PM, Aaryaman Vasishta < jem456.vasishta at gmail.com> wrote: > This patch adds proper delays to maxwell exa shaders. rendercheck tests > seem consistent with/without this patch. I haven't extensively tested > them though. > > Trello: > https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders- > with-proper-delays > > Signe...

Removed explicit depar instructions as they're not used by the blob anymore. Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 5 ++--- src/shader/exac8nv110.fpc | 10 ++++------ src/shader/exacanv110.fp | 5 ++--- src/shader/exacanv110.fpc | 10 ++++------ src/shader/exacmnv110.fp | 5 ++--- src/shader/exacmnv110.fpc | 10 ++++------

Nice work! See my comments below, and double-check if some of them can be applied to the shaders I didn't review yet. I recommend you to test your work because if one sched code is wrong, you are likely going to kill your card and reboot your box. :-) On 06/03/2017 04:16 PM, Aaryaman Vasishta wrote: > v2: Add missing delays > > This patch adds proper delays to maxwell exa shaders. rendercheck tests > seem consistent with/without this patch. I haven't extensive...

On Thu, Jun 8, 2017 at 5:01 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > > > On 06/07/2017 06:58 PM, Aaryaman Vasishta wrote: > >> >> >> On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset < >> samuel.pitoiset at gmail.com <mailto:samuel.pitoiset at gmail.com>> wrote: >> >> Nice work! >> >>...

...insertions(+), 141 deletions(-) diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp index ce78036..7537780 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,24 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0 wt 0x3f) (st 0xd wr 0x0 wt 0x1) (st 0x1 wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0x2 wr 0x1 rd 0x0 wt 0x3) (st 0x1 wr 0x0 wt 0x1) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0...

On 06/07/2017 06:58 PM, Aaryaman Vasishta wrote: > > > On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset > <samuel.pitoiset at gmail.com <mailto:samuel.pitoiset at gmail.com>> wrote: > > Nice work! > > See my comments below, and double-check if some of them can be > applied to the shaders...

On 06/10/2017 09:14 AM, Aaryaman Vasishta wrote: > See the 'wt' on the first fmul in exacanv110.fp, exacmnv110.fp and > exasanv110.fp. Any ideas on what could be causing the first fmul to > require $r0 and/or $r1? 'tex nodep $r4 $r2 0x0 0x1 t2d 0xf' is actually: 'tex nodep $r4:$r7 $r2 0x0 0x1 t2d 0xf' Ve...

...te.c:490 ast_translator_build_path: No translator path: (ending codec is not valid) [Oct  2 07:24:55] WARNING[23961][C-00000000]: translate.c:490 ast_translator_build_path: No translator path: (starting codec is not valid) [Oct  2 07:24:55] WARNING[23961][C-00000000]: chan_pjsip.c:856 chan_pjsip_write: Channel PJSIP/boslwzldi21-00000001 asked to send alaw frame when native formats are (siren7) (rd:alaw->slin16;(alaw at 8000)->(slin at 8000)->(slin at 16000) wr:slin16->alaw;(slin at 16000)->(slin at 8000)->(alaw at 8000)) [Oct  2 07:24:55] WARNING[23961][C-00000000]: chan_...

error viewed: Updating : openssl ####################### [ 1/48] /sbin/ldconfig: /lib/libstdc++-libc6.2-2.so.3 is not an ELF file - it has the wr ong magic bytes at the start. Updating : openssl ####################### [ 1/48] /sbin/ldconfig: /lib/libstdc++-libc6.2-2.so.3 is not an ELF file - it has the wr ong magic bytes at the start. Any one else getting this when you run "yum update" from ssh?? Evans F...

On Mon, Jul 28, 2014 at 12:18:10PM -0700, H. Peter Anvin wrote: > On 07/28/2014 12:04 PM, Eduardo Habkost wrote: > > When CONFIG_PARAVIRT is enabled, the kernel is ignoring exceptions on > > the {rd,wr}msr instructions. This makes serious issues (either on the > > guest kernel, or on the host) be silently ignored, and is different from...

On Mon, Jul 28, 2014 at 12:18:10PM -0700, H. Peter Anvin wrote: > On 07/28/2014 12:04 PM, Eduardo Habkost wrote: > > When CONFIG_PARAVIRT is enabled, the kernel is ignoring exceptions on > > the {rd,wr}msr instructions. This makes serious issues (either on the > > guest kernel, or on the host) be silently ignored, and is different from...