search for: wpr

On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > The GPUs found on Tegra SoCs have registers that can be used to read the > WPR configuration. Use these registers instead of reaching into the > memory controller's register space to read the same information. > > Signed-off-by: Thierry Reding <treding at nvidia.com> > --- > .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +- > .../drm/nouveau/...

...49:57PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > > > From: Thierry Reding <treding at nvidia.com> > > > > The GPUs found on Tegra SoCs have registers that can be used to read the > > WPR configuration. Use these registers instead of reaching into the > > memory controller's register space to read the same information. > > > > Signed-off-by: Thierry Reding <treding at nvidia.com> > > --- > > .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2...

From: Thierry Reding <treding at nvidia.com> The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding <treding at nvidia.com> --- .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +- .../drm/nouveau/nvkm/subdev/secboot/gm20b.c...

This hook can be removed if the function writing the HS descriptor is aware of WPR settings. Let's do that as it allows us to make the ACR descriptor structure private and save some code. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/gm200.c | 95 ++++++++++++++++++++++++--------- drm/nouveau/nvkm/subdev/secboot/gm20b.c...

...uveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -278,75 +278,44 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, } /** - * struct ls_ucode_mgr - manager for all LS falcon firmwares - * @count: number of managed LS falcons - * @wpr_size: size of the required WPR region in bytes - * @img_list: linked list of lsf_ucode_img + * acr_r352_ls_fill_headers - fill WPR and LSB headers of all managed images */ -struct ls_ucode_mgr { - u16 count; - u32 wpr_size; - struct list_head img_list; -}; - -static void -ls_ucode_mgr_init(struct...

The WPR and LSB headers, used to generate the LS blob, may have a different layout and sizes depending on the driver version they come from. Abstract them and confine their use to driver-specific code. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/acr...

...n running blob secboot: remove unneeded ls_ucode_img member secboot: remove ls_ucode_mgr secboot: abstract LS firmware loading functions secboot: safer zeroing of BL descriptors secboot: add missing fields to BL structure secboot: set default error value in error register secboot: fix WPR descriptor generation secboot: add lazy-bootstrap flag falcon: add clear_interrupt function secboot: clear halt interrupt after ACR is run drm/nouveau/include/nvkm/engine/falcon.h | 2 +- drm/nouveau/include/nvkm/subdev/secboot.h | 10 +- drm/nouveau/nvkm/falcon/base.c...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

...witching a HS-capable falcon (typically + * PMU) into HS mode in order to validate the LS firmwares of managed falcons, + * load them, and switch managed falcons into LS mode. Once secure boot + * completes, no falcon remains in HS mode. + * + * Secure boot requires a write-protected memory region (WPR) which can only be + * written by the secure falcon. On dGPU, the driver sets up the WPR region in + * video memory. On Tegra, it is set up by the bootloader and its location and + * size written into memory controller registers. + * + * The secure boot process takes place as follows: + * + * 1) A...

...- */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -/** - * struct lsf_lsb_header - LS firmware header - * @signature: signature to verify the firmware against - * @ucode_off: offset of the ucode blob in the WPR region. The ucode - * blob contains the bootloader, code and data of the - * LS falcon - * @ucode_size: size of the ucode blob, including bootloader - * @data_size: size of the ucode blob data - * @bl_code_size: size of the bootloader code - * @bl_imem_of...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

...before running secboot: remove unneeded ls_ucode_img member secboot: remove ls_ucode_mgr secboot: abstract LS firmware loading functions secboot: safer zeroing of BL descriptors secboot: add missing fields to BL structure secboot: set default error value in error register secboot: fix WPR descriptor generation secboot: add lazy-bootstrap flag secboot: store falcon's DMEM size in secboot structure secboot: clear halt interrupt after ACR is run core: add falcon DMEM read function pmu: add nvkm_pmu_ctor function pmu: make sure the reset hook exists before running it s...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

...ixes this issue. Another issue is that the clock may be running at a rate of 0 Hz. This is unlikely to happen because it internally actually can't run that slow, but explicitly setting the clock rate at probe time does seem to help in some cases. Patch three in this series unifies reading the WPR configuration by getting it from GPU register rather than reaching into the memory controller's register space. This is slightly better because it better separates the two drivers and doesn't require an update everytime the memory controller moves to another register aperture. Patch 4 ensu...

...clude/nvkm/subdev/secboot.h +++ b/drm/nouveau/include/nvkm/subdev/secboot.h @@ -30,6 +30,7 @@ * @base: base IO address of the falcon performing secure boot * @managed_falcons: bitfield of falcons managed by this ACR * @debug_mode: whether the debug or production signatures should be used + * @wpr_set: whether the WPR region is currently set */ struct nvkm_secboot { const struct nvkm_secboot_func *func; @@ -44,6 +45,8 @@ struct nvkm_secboot { u32 wpr_size; bool debug_mode; + + bool wpr_set; }; #define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev) diff --git a/d...

...iommu_fwspec::flags field iommu: Add dummy dev_iommu_fwspec_get() helper drm/nouveau: fault: Add support for GP10B drm/nouveau: tegra: Do not try to disable PCI device drm/nouveau: tegra: Avoid pulsing reset twice drm/nouveau: tegra: Set clock rate if not set drm/nouveau: secboot: Read WPR configuration from GPU registers drm/nouveau: gp10b: Add custom L2 cache implementation drm/nouveau: gp10b: Use correct copy engine .../drm/nouveau/include/nvkm/subdev/fault.h | 1 + .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 + drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-...

...iommu_fwspec::flags field iommu: Add dummy dev_iommu_fwspec_get() helper drm/nouveau: fault: Add support for GP10B drm/nouveau: tegra: Do not try to disable PCI device drm/nouveau: tegra: Avoid pulsing reset twice drm/nouveau: tegra: Set clock rate if not set drm/nouveau: secboot: Read WPR configuration from GPU registers drm/nouveau: gp10b: Add custom L2 cache implementation drm/nouveau: gp10b: Use correct copy engine .../drm/nouveau/include/nvkm/subdev/fault.h | 1 + .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 + drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-...

This series fixes two cases where behavior on secure boot errors could be improved: 1) Patch 2 propages secure-boot errors from GR init, making sure initialization fails as it should. Failure to do so results in a black screen during boot, as reported in FD bug 94990. 2) Patches 3-4 make the absence of required secure firmware files a non-fatal error. The previous behavior was to give up