Displaying 2 results from an estimated 2 matches for "wlentri".
Did you mean:
wlentry
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all,
I have a question about per-operand machine model. I am finding some
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST:
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies.
Thanks for your kind explanation.
Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of