search for: width0

...v30_miptree.c +++ b/src/gallium/drivers/nv30/nv30_miptree.c @@ -56,8 +56,7 @@ nv30_miptree_get_handle(struct pipe_screen *pscreen, if (!mt || !mt->base.bo) return FALSE; - stride = util_format_get_stride(mt->base.base.format, - mt->base.base.width0); + stride = mt->level[0].pitch; return nouveau_screen_bo_get_handle(pscreen, mt->base.bo, stride, handle); } diff --git a/src/gallium/drivers/nv50/nv50_miptree.c b/src/gallium/drivers/nv50/nv50_miptree.c index 7b8dfb8..70e8c77 100644 --- a/src/gallium/drivers/nv50/nv50_miptree.c +++...

...nv50_context *nv50, unsigned vbi, assert(vbi < PIPE_MAX_ATTRIBS); if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) { /* TODO: use min and max instance divisor to get a proper range */ - *base = 0; - *size = nv50->vtxbuf[vbi].buffer.resource->width0; + const uint32_t div = nv50->vertex->min_instance_div[vbi]; + *base = nv50->instance_off * nv50->vtxbuf[vbi].stride; + *size = (nv50->instance_max / div) * nv50->vtxbuf[vbi].stride + + nv50->vertex->vb_access_size[vbi]; +// *base = 0; +// *s...

...= &mt->base; uint offset = 0; - int nr_faces, l; - - nr_faces = 1; + unsigned uniform_pitch = 0; + static int no_swizzle = -1; + if(no_swizzle < 0) + no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE); + + /* Non-uniform pitch textures must be POT */ + if (pt->width0 & (pt->width0 - 1) || + pt->height0 & (pt->height0 - 1) || + pt->depth0 & (pt->depth0 - 1) + ) + uniform_pitch = 1; + + /* All texture formats except compressed ones can be swizzled + * Unsure about depth, let's prevent swizzling for now + */ + if (pt-&...

This patch fixes two issues in nv40_miptree_layout. First, pt->width0 is used, which is the size of the whole texture, while width, which is the size of the mipmap level, should be used. Second, the current code does not 64-byte align the pitch of swizzled textures. However, on my NV40 this causes a pgraph error regarding the pitch register (and sometimes a system l...

...= &mt->base; uint offset = 0; - int nr_faces, l; - - nr_faces = 1; + unsigned uniform_pitch = 0; + static int no_swizzle = -1; + if(no_swizzle < 0) + no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE); + + /* Non-uniform pitch textures must be POT */ + if (pt->width0 & (pt->width0 - 1) || + pt->height0 & (pt->height0 - 1) || + pt->depth0 & (pt->depth0 - 1) + ) + uniform_pitch = 1; + + /* All texture formats except compressed ones can be swizzled + * Unsure about depth, let's prevent swizzling for now + */ + if (pt-&...

...& 0x1f)); > + /* must be 2D texture without mip maps */ > + tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH; > + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP; > + tic[3] |= mt->level[0].pitch >> 5; > + tic[4] |= mt->base.base.width0 - 1; > + tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT; > + tic[5] |= mt->base.base.height0 - 1; > + } > + tic[1] = address; > + tic[2] |= address >> 32; > + tic[6] = 0; > + tic[7] = 0; > + return &view...

...(!(mt->level[0].pitch & 0x1f)); + /* must be 2D texture without mip maps */ + tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH; + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP; + tic[3] |= mt->level[0].pitch >> 5; + tic[4] |= mt->base.base.width0 - 1; + tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT; + tic[5] |= mt->base.base.height0 - 1; + } + tic[1] = address; + tic[2] |= address >> 32; + tic[6] = 0; + tic[7] = 0; + return &view->pipe; + } + + tic[2] = GM107_T...

...t; + /* must be 2D texture without mip maps */ >> + tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH; >> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP; >> + tic[3] |= mt->level[0].pitch >> 5; >> + tic[4] |= mt->base.base.width0 - 1; >> + tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT; >> + tic[5] |= mt->base.base.height0 - 1; >> + } >> + tic[1] = address; >> + tic[2] |= address >> 32; >> + tic[6] = 0; >> + tic[7] = 0;...

https://bugs.freedesktop.org/show_bug.cgi?id=93004 Bug ID: 93004 Summary: Guild Wars 2 crash on nouveau DX11 cards Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at

On Thu, Sep 3, 2015 at 7:25 AM, Hans de Goede <hdegoede at redhat.com> wrote: > On nv3x we will likely end up using the cpu to do color resolving for msaa > blits. Disable msaa on these cards so that we do not end up using the cpu. Actually the CPU fallback won't do scaled, so it's stuck with SIFM or assert(false). Which isn't great, but... it's what the HW does. I

...ater on buffer->num_planes = 2; > + > + memset(&templ, 0, sizeof(templ)); > + templ.target = PIPE_TEXTURE_2D_ARRAY; > + templ.depth0 = 1; > + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; > + templ.format = PIPE_FORMAT_R8_UNORM; > + templ.width0 = align(template->width, 2); > + templ.height0 = align(template->height, 4) / 2; > + templ.flags = NV50_RESOURCE_FLAG_VIDEO; > + templ.array_size = 2; > + > + cfg.nv50.tile_mode = 0x20; > + cfg.nv50.memtype = 0x70; > + > + buffer->resources[0] = pipe-&gt...

Hi All, Here is a bunch of fixes for nv30 cards, the first patch is a resend of a patch I send a while back. AFAICT that one is ready for merging, but it is not entirely clear to me what the process is for getting (nouveau) mesa patches merged. Should I request commit rights, and push my own patches once they have been reviewed ? Regards, Hans

...r :) > >> + >> + memset(&templ, 0, sizeof(templ)); >> + templ.target = PIPE_TEXTURE_2D_ARRAY; >> + templ.depth0 = 1; >> + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; >> + templ.format = PIPE_FORMAT_R8_UNORM; >> + templ.width0 = align(template->width, 2); >> + templ.height0 = align(template->height, 4) / 2; >> + templ.flags = NV50_RESOURCE_FLAG_VIDEO; >> + templ.array_size = 2; >> + >> + cfg.nv50.tile_mode = 0x20; >> + cfg.nv50.memtype = 0x70; >> + >> + bu...

...t;>> + memset(&templ, 0, sizeof(templ)); >>> + templ.target = PIPE_TEXTURE_2D_ARRAY; >>> + templ.depth0 = 1; >>> + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; >>> + templ.format = PIPE_FORMAT_R8_UNORM; >>> + templ.width0 = align(template->width, 2); >>> + templ.height0 = align(template->height, 4) / 2; >>> + templ.flags = NV50_RESOURCE_FLAG_VIDEO; >>> + templ.array_size = 2; >>> + >>> + cfg.nv50.tile_mode = 0x20; >>> + cfg.nv50.memtype = 0x70; &g...

...format); + + assert(pt->last_level == 0); + assert(mt->ms_x == 0 && mt->ms_y == 0); + assert(!util_format_is_compressed(pt->format)); + + mt->layout_3d = pt->target == PIPE_TEXTURE_3D; + + mt->level[0].tile_mode = 0x20; + mt->level[0].pitch = align(pt->width0 * blocksize, 64); + mt->total_size = align(pt->height0, 16) * mt->level[0].pitch * (mt->layout_3d ? pt->depth0 : 1); + + if (pt->array_size > 1) { + mt->layer_stride = align(mt->total_size, NV50_TILE_SIZE(0x20)); + mt->total_size = mt->layer_stride * p...

...info Every OpenGL application that wants to use a depth buffer always crashes, including glxgears: glxgears: dri2.c:906: dri2_allocate_textures: Assertion `*zsbuf' failed. I debugged the assertion with gdb: templ structure contents passed to resource_create(): $2 = {reference = {count = 0}, width0 = 300, height0 = 300, depth0 = 1, array_size = 1, format = PIPE_FORMAT_Z24X8_UNORM, target = PIPE_TEXTURE_2D, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 1, flags = 0, next = 0x0, screen = 0x0} In nv50_miptree_create() in gallium/drivers/nouveau/nv50/nv50_miptree....

...format); + + assert(pt->last_level == 0); + assert(mt->ms_x == 0 && mt->ms_y == 0); + assert(!util_format_is_compressed(pt->format)); + + mt->layout_3d = pt->target == PIPE_TEXTURE_3D; + + mt->level[0].tile_mode = 0x20; + mt->level[0].pitch = align(pt->width0 * blocksize, 64); + mt->total_size = align(pt->height0, 16) * mt->level[0].pitch * (mt->layout_3d ? pt->depth0 : 1); + + if (pt->array_size > 1) { + mt->layer_stride = align(mt->total_size, NV50_TILE_SIZE(0x20)); + mt->total_size = mt->layer_stride * p...

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for

From: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> --- src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h