Displaying 3 results from an estimated 3 matches for "wide32".
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2011 Sep 23
2
[LLVMdev] Registers and isel type inference
So I tried adding a new register class to the x86 target:
def WIDE32 : RegisterClass<"X86", [i32, f32], 32, (add GR32, FR32)>;
I thought this would be a harmless thing to do since the new register class is not being referenced anywhere. I was wrong, it caused all kinds of assertion failures from tablegen's isel pattern generator.
It appears th...
2011 Sep 23
0
[LLVMdev] Registers and isel type inference
...lesen <stoklund at 2pi.dk> writes:
> It appears that tablegen is inferring the 'type' of an individual
> register by enumerating all the register classes it appears in. Some
> things, like using implicit defs in SDNodes, only works for registers
> with a unique type. My WIDE32 class caused GR32 registers to no
> longer have a unique type, breaking the world.
I can't remeber the specific situation, but I remember running into
this kind of problem before.
> This seems too fragile to me.
Yes, it is. :(
> - Disable type inference for individual registers e...
2011 Sep 23
2
[LLVMdev] Registers and isel type inference
...2pi.dk> writes:
>
>> It appears that tablegen is inferring the 'type' of an individual
>> register by enumerating all the register classes it appears in. Some
>> things, like using implicit defs in SDNodes, only works for registers
>> with a unique type. My WIDE32 class caused GR32 registers to no
>> longer have a unique type, breaking the world.
>
> I can't remeber the specific situation, but I remember running into
> this kind of problem before.
>
>> This seems too fragile to me.
>
> Yes, it is. :(
>
>> - Di...