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...it can solve my problem. The issue itself isn't with branching, as I can handle branches fairly well in my custom pass(see the before and after dot files attached). I can take a bunch of branches and construct high level control flow for my backend since I have no ability to do goto/jump, only whileloop and ifs. So analyzing the branch's isn't the problem. The problem comes with emit'ing the code. Even though I've renumbered the blocks and re-ordered the CFG into a more sane control flow. The code emitter still processes the blocks in the old order. So instead of going from 0-5, it...

On Oct 14, 2008, at 9:16 AM, Villmow, Micah wrote: > But, the branch folding pass, or whatever passes are supposed to > reorder the blocks based on the CFG, are not doing so in this case. > Otherwise there is no way that blocks 2 and 4 should be printing out > before blocks 3 & 5. Renumber blocks just seems to reorder the > values based on their pre-set block number,

...it can solve my problem. The issue itself isn't with branching, as I can handle branches fairly well in my custom pass(see the before and after dot files attached). I can take a bunch of branches and construct high level control flow for my backend since I have no ability to do goto/jump, only whileloop and ifs. So analyzing the branch's isn't the problem. The problem comes with emit'ing the code. Even though I've renumbered the blocks and re-ordered the CFG into a more sane control flow. The code emitter still processes the blocks in the old order. So instead of going from 0-5, it...

...by default: SingleSource/UnitTests: SetjmpLongjmp/C++/C++Catch.cpp SetjmpLongjmp/C++/C/FarJump.c SetjmpLongjmp/C++/C/Looping.c SetjmpLongjmp/C++/C/MultipleSetjmp.c SetjmpLongjmp/C++/C/SimpleCTest.c SetjmpLongjmp/C++/C/WhileLoop.c SignlessTypes/cast-bug.c SignlessTypes/cast.cpp SignlessTypes/cast2.cpp SignlessTypes/ccc.c SignlessTypes/div.c SignlessTypes/factor.c SignlessTypes/rem.c SignlessTypes/shr.c 4) are the...

But, the branch folding pass, or whatever passes are supposed to reorder the blocks based on the CFG, are not doing so in this case. Otherwise there is no way that blocks 2 and 4 should be printing out before blocks 3 & 5. Renumber blocks just seems to reorder the values based on their pre-set block number, but when the CFG is modified these number should modified also to follow the new

...ase AMDGPU::BREAK_LOGICALNZ_f32: > + case AMDGPU::CONTINUE_LOGICALNZ_f32: > + case AMDGPU::IF_LOGICALNZ_i32: > + case AMDGPU::IF_LOGICALZ_f32: > + case AMDGPU::ELSE: > + case AMDGPU::ENDIF: > + case AMDGPU::ENDLOOP: > + case AMDGPU::IF_LOGICALNZ_f32: > + case AMDGPU::WHILELOOP: > + return true; > + } > +} > + > +void AMDGPU::utilAddLiveIn(MachineFunction * MF, > + MachineRegisterInfo & MRI, > + const TargetInstrInfo * TII, > + unsigned physReg, unsigned virtReg)...

...2_Z<def> = MOV 1, 0, 0, 0, %C1_Z, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0, %T2_XYZW<imp-def> > %T2_W<def> = MOV 1, 0, 0, 0, %C1_W, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0, %T2_XYZW<imp-def> > %T3_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0 > WHILELOOP > %T3_Y<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %T3_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0 > %PREDICATE_BIT<def> = PRED_SETE_INT 1, 0, 0, 0, 0, 0, %T3_Y, 0, 0, 0, %ZERO, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0 > BREAK_LOGICALZ_i32 %PREDICATE_BIT > %T3_Y<def> = MOV 1...

...;imp-def> %T2_Z<def> = MOV 1, 0, 0, 0, %C1_Z, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0, %T2_XYZW<imp-def> %T2_W<def> = MOV 1, 0, 0, 0, %C1_W, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0, %T2_XYZW<imp-def> %T3_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0 WHILELOOP %T3_Y<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %T3_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0 %PREDICATE_BIT<def> = PRED_SETE_INT 1, 0, 0, 0, 0, 0, %T3_Y, 0, 0, 0, %ZERO, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0 BREAK_LOGICALZ_i32 %PREDICATE_BIT %T3_Y<def> = MOV 1, 0, 0, 0, %ALU_LITE...