Displaying 7 results from an estimated 7 matches for "whilebody".
2008 Oct 01
2
[LLVMdev] complex branching generation
...=1]
%tobool24 = fcmp une float %y, 0.000000e+000 ; <i1>
[#uses=2]
%or.cond5 = and i1 %tobool3, %tobool24 ; <i1> [#uses=1]
br i1 %or.cond5, label %bb.nph, label %whileexit
bb.nph: ; preds = %entry
br i1 %tobool24, label %whilebody.us, label %whilebody
whilebody.us: ; preds = %whilebody.us, %bb.nph
...code here...
br i1 %phitmp, label %whilebody.us, label %whileexit
whilebody: ; preds = %bb.nph
...code here...
br label %whileexit
whileexit: ; preds = %whilebo...
2008 Oct 01
0
[LLVMdev] complex branching generation
...0000e+000 ; <i1>
> [#uses=2]
>
> %or.cond5 = and i1 %tobool3, %tobool24 ; <i1> [#uses=1]
>
> br i1 %or.cond5, label %bb.nph, label %whileexit
>
>
>
> bb.nph: ; preds = %entry
>
> br i1 %tobool24, label %whilebody.us, label %whilebody
>
>
>
> whilebody.us: ; preds = %whilebody.us, %bb.nph
>
> …code here…
>
> br i1 %phitmp, label %whilebody.us, label %whileexit
>
>
>
> whilebody: ; preds = %bb.nph
>
> …code here…
>
> br lab...
2010 Jan 28
2
[LLVMdev] llc generated machine assembly code for NASM
...t;i32> [#uses=1]
%2 = icmp ne i32 %1, 0 ; <i1> [#uses=1]
br i1 %2, label %then, label %else
then: ; preds = %entry
store i32 0, i32* %lv
br label %while
while: ; preds = %whilebody,
%then
%gv = load i32* @gv ; <i32> [#uses=1]
%3 = icmp ugt i32 %gv, 0 ; <i1> [#uses=1]
%4 = zext i1 %3 to i32 ; <i32> [#uses=1]
%5 = icmp ne i32 %4, 0 ; <i1> [#uses=1...
2017 Sep 16
2
assertion triggered since update to llvm 5
...; preds = %OverflowOk6,
%Entry
%1 = load i64, i64* %src_index, align 8, !dbg !74
%2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg !75
%3 = load i64, i64* %2, align 8, !dbg !75
%4 = icmp ult i64 %1, %3, !dbg !76
br i1 %4, label %WhileBody, label %WhileEnd, !dbg !76
WhileBody: ; preds = %WhileCond
%5 = load i64, i64* %index, align 8, !dbg !77
%6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5), !dbg
!78
%7 = extractvalue { i64, i1 } %6, 0, !dbg !78
%8 = extractvalue { i64,...
2017 Sep 17
2
assertion triggered since update to llvm 5
...%Entry
>> %1 = load i64, i64* %src_index, align 8, !dbg !74
>> %2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg !75
>> %3 = load i64, i64* %2, align 8, !dbg !75
>> %4 = icmp ult i64 %1, %3, !dbg !76
>> br i1 %4, label %WhileBody, label %WhileEnd, !dbg !76
>>
>> WhileBody: ; preds = %WhileCond
>> %5 = load i64, i64* %index, align 8, !dbg !77
>> %6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5),
>> !dbg !78
>> %7 = extractvalue {...
2017 Sep 17
4
assertion triggered since update to llvm 5
..., align 8, !dbg !74
>>>> %2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg
>>>> !75
>>>> %3 = load i64, i64* %2, align 8, !dbg !75
>>>> %4 = icmp ult i64 %1, %3, !dbg !76
>>>> br i1 %4, label %WhileBody, label %WhileEnd, !dbg !76
>>>>
>>>> WhileBody: ; preds = %WhileCond
>>>> %5 = load i64, i64* %index, align 8, !dbg !77
>>>> %6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5),
>>>>...
2017 Sep 17
2
assertion triggered since update to llvm 5
...>>>>> %2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg
>>>>> !75
>>>>> %3 = load i64, i64* %2, align 8, !dbg !75
>>>>> %4 = icmp ult i64 %1, %3, !dbg !76
>>>>> br i1 %4, label %WhileBody, label %WhileEnd, !dbg !76
>>>>>
>>>>> WhileBody: ; preds = %WhileCond
>>>>> %5 = load i64, i64* %index, align 8, !dbg !77
>>>>> %6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5),...