search for: westmere

...roadwell-noTSX' CPU model. LibVirt appears to be comparing the source and destination host CPUs, instead of guest VM and destination host CPUs. The VM is configured with a common set CPU features that are compatible with both (see below) and can run on both hosts without issue. The hosts have Westmere and Broadwell CPUs (See host CPU capabilities below). The VM can be booted on the Westmere host, successfully live migrated to the Broadwell host, but then throws the above error when we attempt to live migrating back to the Westmere host. Due to how our Westmere hosts were configured in OpenStack...

...used If I review the qemu log for that particular domain, I see that my CPU has been changed to this: -cpu kvm64,+lahf_lm,+popcnt,+sse4.2,+sse4.1,+ssse3 (in other places, I see it set to core2duo rather than kvm64) However, it *should* be Nehalem. For some background, I'm running kvm on a westmere proc, which is the successor to Nehalem. I'm specifying Nehalem as the target platform, though, to make it easier to migrate to another server if necessary. I do have this same problem if I set this to Westmere, though, so it's not unique to Nehalem. As for support and capabilities, libv...

Hi all. I'm looking for an advice on how to deal with inefficient code generation for Intel Nehalem/Westmere architecture on 64-bit platform for the attached test.cpp (LLVM IR is in test.cpp.ll). The inner loop has 11 iterations and eventually unrolled. Test.lea.s is the assembly code of the outer loop. It simply has 11 loads, 11 FP add, 11 FP mull, 1 FP store and lea+mov for index computation, cmp and ju...

...or my version -- also attached is the test code. I found that booting big machines is tediously slow so I lifted the whole lot to userspace. I measure the cycles spend in arch_spin_lock() + arch_spin_unlock(). The machines used are a 4 node (2 socket) AMD Interlagos, and a 2 node (2 socket) Intel Westmere-EP. AMD (ticket) AMD (qspinlock + pending + opt) Local: Local: 1: 324.425530 1: 324.102142 2: 17141.324050 2: 620.185930 3: 52212.232343 3: 25242.574661 4: 93136.458314 4: 47982.037866 6: 167967.455965 6: 95345.011864 8: 245402....

...or my version -- also attached is the test code. I found that booting big machines is tediously slow so I lifted the whole lot to userspace. I measure the cycles spend in arch_spin_lock() + arch_spin_unlock(). The machines used are a 4 node (2 socket) AMD Interlagos, and a 2 node (2 socket) Intel Westmere-EP. AMD (ticket) AMD (qspinlock + pending + opt) Local: Local: 1: 324.425530 1: 324.102142 2: 17141.324050 2: 620.185930 3: 52212.232343 3: 25242.574661 4: 93136.458314 4: 47982.037866 6: 167967.455965 6: 95345.011864 8: 245402....

...essor-l5630-12m-cache-2-13-ghz-5-86-gt-s-intel-qpi.html 12M Cache, 2.13 GHz, 5.86 GT/s Intel? QPI https://ark.intel.com/content/www/us/en/ark/products/52274/intel-xeon-processor-e3-1245-8m-cache-3-30-ghz.html 8M Cache, 3.30 GHz The ?generations? I mentioned are: Code NameProducts formerly Westmere EP <https://ark.intel.com/content/www/us/en/ark/products/codename/54534/westmere-ep.html> Code NameProducts formerly Sandy Bridge <https://ark.intel.com/content/www/us/en/ark/products/codename/29900/sandy-bridge.html> Westmere systems used DDR at 800/1066MHz. Sandy Bridge systems us...

This sounds like llvm.org/pr13320. On 17 September 2013 18:20, Bader, Aleksey A <aleksey.a.bader at intel.com> wrote: > Hi all. > > > > I’m looking for an advice on how to deal with inefficient code generation > for Intel Nehalem/Westmere architecture on 64-bit platform for the attached > test.cpp (LLVM IR is in test.cpp.ll). > > The inner loop has 11 iterations and eventually unrolled. > > Test.lea.s is the assembly code of the outer loop. It simply has 11 loads, > 11 FP add, 11 FP mull, 1 FP store and lea+mov for...

...being chosen)? So a question: as a packager and distributor, do I need to build on a processor that has both SSE4.2 and AVX2 instructions enabled? And if one or both of these are not enabled, will the resulting build contain fewer parsers? > Optimized versions can be disabled with --disable-westmere (SSE4.2) and > --disable-haswell (AVX2) if desired btw. Thanks for providing these options. But it would help users to know the effects of enabling/disabling these options, so that they can make an informed choice. Another question: if a user has a binary containing all three parsers, and w...

...ing fine with libvirt using qemu+kvm, however I observed that <cpu mode='host-model'> is not exposing avx and avx2 instruction set to the guest Linux instance. Google Cloud platform claims the CPU model of the host compute instance is Broadwell, however libvirt capabilities maps it to Westmere-IBRS and it has avx and avx2 features, yet host-model is not exposing those. As a workaround, I am using <cpu mode='host-passthrough'>, but I would like to know what is going wrong here? I can also share the output of cpuid of the host system, if that helps. I am not sure whether...

...hey call "NUMA split mode" should be disabled in the >> BIOS of the Z800 workstation when running Linux. They are reasoning >> that Linux kernels do not support this feature and even might not boot >> if it?s enabled. > > hmm, that workstation is a dual Xeon 56xx (Westmere-EP, derived from > Nehalem), new in 2010 > >> Since it apparently was years ago since they made this statement, I?m >> wondering if I should still leave this feature disabled or not. More >> recent kernels might support it, and it?s supposed to improve >> performance....

...ee Intel #'s below) > Do you have perf data on Intel CPUs? Good idea -- I ran some tests on a couple of Intel platforms: (these are perf data from sample runs; for each I ran many runs, the numbers were pretty stable except for Haswell-EP cross-socket) One-socket Intel Xeon W3690 ("Westmere"), 3.46 GHz; core turbo disabled ======================================================================= (note -- w/ core turbo disabled, performance is _very_ stable; variance of < 0.5% run-to-run; figure of merit is "seconds elapsed" here) * Producer / consumer bound to Hypert...

...ee Intel #'s below) > Do you have perf data on Intel CPUs? Good idea -- I ran some tests on a couple of Intel platforms: (these are perf data from sample runs; for each I ran many runs, the numbers were pretty stable except for Haswell-EP cross-socket) One-socket Intel Xeon W3690 ("Westmere"), 3.46 GHz; core turbo disabled ======================================================================= (note -- w/ core turbo disabled, performance is _very_ stable; variance of < 0.5% run-to-run; figure of merit is "seconds elapsed" here) * Producer / consumer bound to Hypert...

...gt; This sounds like llvm.org/pr13320. > >> On 17 September 2013 18:20, Bader, Aleksey A <aleksey.a.bader at intel.com> wrote: >> Hi all. >> >> >> >> I’m looking for an advice on how to deal with inefficient code generation >> for Intel Nehalem/Westmere architecture on 64-bit platform for the attached >> test.cpp (LLVM IR is in test.cpp.ll). >> >> The inner loop has 11 iterations and eventually unrolled. >> >> Test.lea.s is the assembly code of the outer loop. It simply has 11 loads, >> 11 FP add, 11 FP mull,...

Hello, 1. Can you please tell me how can I find the type of my Intel Xeon?I see in LLVM code that Intel Xeon processors can be of type "core2", "penryn", "westmere", "skylake". 2. I also see that "skylake" can be a type and a subtype as well.How can I find out the subtype of my architecture? Looking forward for you answer. Thank you.Iulia On Sunday, June 4, 2017 7:11 PM, Tim Northover <t.p.northover at gmail.com> wrote:...

...worse in a virtualized guest. If a waiting VCPU deschedules and has to be kicked to grab a lock then it is very likely to lose a race with another running VCPU trying to take a lock (since it takes time for the VCPU to be rescheduled). > With the unfair locking activated on bare metal 4-socket Westmere-EX > box, the execution times (in ms) of a spinlock micro-benchmark were > as follows: > > # of Ticket Fair Unfair > tasks lock queue lock queue lock > ------ ------- ---------- ---------- > 1 135 135 137 > 2...

...worse in a virtualized guest. If a waiting VCPU deschedules and has to be kicked to grab a lock then it is very likely to lose a race with another running VCPU trying to take a lock (since it takes time for the VCPU to be rescheduled). > With the unfair locking activated on bare metal 4-socket Westmere-EX > box, the execution times (in ms) of a spinlock micro-benchmark were > as follows: > > # of Ticket Fair Unfair > tasks lock queue lock queue lock > ------ ------- ---------- ---------- > 1 135 135 137 > 2...

I''m trying to use xenoprof in my machine (xeon x5650, westmere). While oprof works for this machine correctly, xenoprof doesn''t work properly. I want to use xenoprof in NMI mode (which is the opposite side of timer mode, right?) However, kernel message always shows that xenoprof works in the timer mode only. Is there any restriction...

Hello Everyone: We can't create vm on a physical server with 64 CPU(as reported by /proc/cpuinfo). The error message is: "cannot set CPU affinity on process 0" The following is the capabilities detected by libvirt: <arch>x86_64</arch> <model>Westmere</model> <vendor>Intel</vendor> <topology sockets='4' cores='10' threads='2'/> I wonder if libvirt uses incorrect CPU topology information to set process affinity which lead to the error above. -------------- next part -------------- An HT...

...a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index fa04c38..d221316 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -285,7 +285,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() { (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX (Family == 6 && Model == 0x2A) || // SandyBridge (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E* - (Family == 6 && Model == 0x3A))) {// IvyBridge + (Family == 6 && Model == 0x3A) || // IvyBridge +...

...logged in syslog frequently. 2012-06-21T09:03:10.754413+00:00 (none) kernel: [ 8659.067243] usb 2-1.4: usbfs: USBDEVFS_CONTROL failed cmd bcmxcp_usb rqt 66 rq 13 len 4 ret -110 I believe that these indicate that the USB driver is timing out USB messages to the UPS. The identical setup running on a Westmere + Tylersburg + ICH10R works fine but on that platform the USB connection is USB 1.1. Thanks, Rich Wrenn -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.alioth.debian.org/pipermail/nut-upsuser/attachments/20120624/85192d6a/attachment.html>