Displaying 5 results from an estimated 5 matches for "w30".
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2019 Jul 26
2
Stackmap offset computation on AArch64
...ce(1)* %ptr)
ret i32 addrspace(1)* %ptr
}
This gets emitted as the following assembly code:
test: // @test
.cfi_startproc
// %bb.0: // %entry
str x30, [sp, #-16]! // 8-byte Folded Spill
.cfi_def_cfa_offset 16
.cfi_offset w30, -16
str x0, [sp, #8]
bl return_i1
.Ltmp0:
ldr x0, [sp, #8]
ldr x30, [sp], #16 // 8-byte Folded Reload
ret
.Lfunc_end0:
.size test, .Lfunc_end0-test
.cfi_endproc
The generated stackmap indicates that %ptr is located at offset -8 from the stack pointer, instead of the expected 8. Af...
2019 Jul 31
0
Stackmap offset computation on AArch64
...de:
>>>
>>> test: // @test
>>> .cfi_startproc
>>> // %bb.0: // %entry
>>> str x30, [sp, #-16]! // 8-byte Folded Spill
>>> .cfi_def_cfa_offset 16
>>> .cfi_offset w30, -16
>>> str x0, [sp, #8]
>>> bl return_i1
>>> .Ltmp0:
>>> ldr x0, [sp, #8]
>>> ldr x30, [sp], #16 // 8-byte Folded Reload
>>> ret
>>> .Lfunc_end0:
>>> .size test, .Lfunc_end0-test
>>> .cfi_endproc
>...
2017 Jan 11
2
HW loads wider than int
...Grosbach via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> ARM64 is like this. I suggest having a look at that backend (lib/Target/AArch64) and how it deals with implicit zeroing of the upper bits of the X registers.
ARM64 has a separate name for the registers as 32-bit values though
(W0-W30 rather than X0-X30). I could easily see DAG ISel throwing a
fit without that.
First thing I'd try would be adding the 64-bit registers as a valid
class for i32 ("addRegisterClass(MVT::i32, GPR64)"). If that works,
you're good to go; if not, it should be possible add fake 32-bit
r...
2020 Jun 22
3
Hardware ASan Generating Unknown Instruction
Hi,
I am trying to execute a simple hello world program compiled like so:
path/to/compiled/clang -o test --target=aarch64-linux-gnu
-march=armv8.5-a -fsanitize=hwaddress
--sysroot=/usr/aarch64-linux-gnu/
-L/usr/lib/gcc/aarch64-linux-gnu/10.1.0/ -g test.c
However, when I look at the disassembly, there is an unknown
instruction listed at 0x2d51c:
000000000002d4c0 main:
2d4c0: ff c3 00 d1
2017 Jan 11
5
HW loads wider than int
I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register.
So for a basic 'a = b + c' example, we get
%0 = load i32, i32* @b, align 4, !tbaa !1
%1