search for: vvmx

...nested vcpu, we need to switch the vmx->vmcs back to the L1 and let the vcpu_destroy() logic to free the L1 VMCS page. Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com> --- xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/hvm/vmx/vmx.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 11 +++++++++++ xen/include/asm-x86/hvm/hvm.h | 1 + xen/include/asm-x86/hvm/vmx/vvmx.h | 1 + 5 files changed, 18 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 7f8a025..0576a24 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen...

...store the launched vvmcs for L1 VMM nested vmx: use VMREAD/VMWRITE to construct vVMCS if enabled VMCS shadowing nested vmx: optimize for bulk access of virtual VMCS nested vmx: enable VMCS shadowing feature xen/arch/x86/hvm/vmx/vmcs.c | 97 +++++++++++++++- xen/arch/x86/hvm/vmx/vvmx.c | 234 +++++++++++++++++++++++++++++++----- xen/include/asm-x86/hvm/vmx/vmcs.h | 23 ++++- xen/include/asm-x86/hvm/vmx/vvmx.h | 22 +++- 4 files changed, 339 insertions(+), 37 deletions(-)

...g <yang.z.zhang@Intel.com> With virtual unrestricted guest feature, L2 guest is allowed to run with PG cleared. Also, allow PAE not set during virtual vmexit emulation. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/hvm.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 7203184..481cb71 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1732,7 +1732,8 @@ int hvm_set_cr0(unsigned long value) { if ( v->...

..._ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page fault error code match and mask nested vmx: fix CR0/CR4 emulation xen/arch/x86/hvm/vmx/vvmx.c | 136 +++++++++++++++++++++++++++++------- xen/include/asm-x86/hvm/vmx/vmcs.h | 2 + 2 files changed, 112 insertions(+), 26 deletions(-)

...in vmcs02 Nested VMX: Update APIC-v(RVI/SVI) when vmexit to L1 xen/arch/x86/hvm/irq.c | 2 +- xen/arch/x86/hvm/vlapic.c | 24 +++++++++++++----- xen/arch/x86/hvm/vmx/intr.c | 9 +++++- xen/arch/x86/hvm/vmx/vmx.c | 14 ++++++---- xen/arch/x86/hvm/vmx/vvmx.c | 45 ++++++++++++++++++++++++++++++++++++ xen/include/asm-x86/hvm/vlapic.h | 3 +- xen/include/asm-x86/hvm/vmx/vmx.h | 2 +- xen/include/asm-x86/hvm/vmx/vvmx.h | 1 + 8 files changed, 82 insertions(+), 18 deletions(-)

...to nested VMM. xen/arch/x86/hvm/hvm.c | 7 +- xen/arch/x86/hvm/svm/nestedsvm.c | 31 +++ xen/arch/x86/hvm/svm/svm.c | 3 +- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 76 +++++--- xen/arch/x86/hvm/vmx/vvmx.c | 208 ++++++++++++++++++- xen/arch/x86/mm/guest_walk.c | 12 +- xen/arch/x86/mm/hap/Makefile | 1 + xen/arch/x86/mm/hap/nested_ept.c | 345 +++++++++++++++++++++++++++++++ xen/arch/x86/mm/hap/nested_hap.c | 79 +++---- xen/arch/x86/mm/mm-l...

...2012 04:11:08 +0800 Subject: [PATCH 2/2] Nested: VM_ENTRY_IA32E_MODE shouldn''t be in default1 class for IA32_VM_ENTRY_CTLS_MSR. If set to 1, L2 guest''s paging mode maybe mis-judged and mis-set. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> --- xen/arch/x86/hvm/vmx/vvmx.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 8e005cd..55781e9 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1334,7 +1334,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u...

...into L1 VMM for handling. Besides, this commit fixes an issue for apic access page, if L1 VMM didn''t enable this feature, we need to fill zero into the shadow VMCS. Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com> --- xen/arch/x86/hvm/vmx/intr.c | 4 +++- xen/arch/x86/hvm/vmx/vvmx.c | 43 +++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/intr.c b/xen/arch/x86/hvm/vmx/intr.c index 535248a..c5c503e 100644 --- a/xen/arch/x86/hvm/vmx/intr.c +++ b/xen/arch/x86/hvm/vmx/intr.c @@ -324,7 +324,9 @@ void...

...#39;t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/vmx/vvmx.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index cecc72f..879af58 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1815,6 +1815,7 @@ int nvmx_msr_read_intercept(unsigned in...

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

while doing "while xm migrate --live domU localhost;do sleep 1;done" I just got the crash shown below. And it can be reproduced. The guest has 2 vcpus and 512mb, it runs pvops 3.7.9 (XEN) ----[ Xen-4.3.26579-20130219.172714 x86_64 debug=n Not tainted ]---- (XEN) CPU: 14 (XEN) RIP: e008:[<ffff82c4c01dd197>] nvmx_vcpu_destroy+0xb7/0x150 (XEN) RFLAGS: 0000000000010282

...87,7 +87,7 @@ nestedhvm_vcpu_initialise(struct vcpu *v void nestedhvm_vcpu_destroy(struct vcpu *v) { - if ( nestedhvm_enabled(v->domain) && hvm_funcs.nhvm_vcpu_destroy ) + if ( hvm_funcs.nhvm_vcpu_destroy ) hvm_funcs.nhvm_vcpu_destroy(v); } --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -62,7 +62,7 @@ int nvmx_vcpu_initialise(struct vcpu *v) if ( !nvcpu->nv_n2vmcx ) { gdprintk(XENLOG_ERR, "nest: allocation for shadow vmcs failed\n"); - goto out; + return -ENOMEM; } /* non-root VMREAD/VMWRITE...

...le iff running in long mode. */ - hvm_get_segment_register(v, x86_seg_cs, &cs); + vmx_get_segment_register(v, x86_seg_cs, &cs); if ( cs.attr.fields.l ) *edx |= cpufeat_mask(X86_FEATURE_SYSCALL); else --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -291,8 +291,6 @@ static int vmx_inst_check_privilege(stru struct vcpu *v = current; struct segment_register cs; - hvm_get_segment_register(v, x86_seg_cs, &cs); - if ( vmxop_check ) { if ( !(v->arch.hvm_vcpu.guest_cr[0]...

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

This set of patches converts the way frames gets created from using PUSHes/POPs to using MOVes, thus allowing (in certain cases) to avoid saving/restoring part of the register set. While the place where the (small) win from this comes from varies between CPUs, the net effect is a 1 to 2% reduction on a combined interruption entry and exit when the full state save can be avoided. 1: use MOV