Displaying 3 results from an estimated 3 matches for "vunpcklp".
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vunpcklps
2011 Feb 25
2
[LLVMdev] X86 LowerVECTOR_SHUFFLE Question
...this code:
if (X86::isUNPCKLMask(SVOp))
getTargetShuffleNode(getUNPCKLOpcode(VT) dl, VT, V1, V2, DAG);
why would this not be:
if (X86::isUNPCKLMask(SVOp))
return SVOp;
I'm trying to add support for VUNPCKL and am getting into trouble
because the existing code ends up creating:
VUNPCKLPS
load
load
which is badness come selection time. Legalize doesn't get a chance to
look below the target shuffle node to see that there are two memory
operands.
Back in the 2.7 days, we used to just return the shuffle as is if it was
already legal. Why the change to create a target node?...
2011 Feb 26
0
[LLVMdev] X86 LowerVECTOR_SHUFFLE Question
...de(VT) dl, VT, V1, V2, DAG);
>
> why would this not be:
>
> if (X86::isUNPCKLMask(SVOp))
> return SVOp;
Ok, I discovered that Bruno did this in revisions 112934, 112942 and
113020 but the logs don't really make clear why. I did figure out that
I needed new SDNode defs for VUNPCKLPSY and VUNPCKLPDY and corresponding
patterns. Once I added them everything started working.
I found this all very confusing because it appears there are now two
ways to match certain shuffle instructions in .td files: one through the
traditional shuffle operators like unpckl and shufp and another...
2011 Feb 26
2
[LLVMdev] X86 LowerVECTOR_SHUFFLE Question
...gt;> why would this not be:
>>
>> if (X86::isUNPCKLMask(SVOp))
>> return SVOp;
>
> Ok, I discovered that Bruno did this in revisions 112934, 112942 and
> 113020 but the logs don't really make clear why. I did figure out that
> I needed new SDNode defs for VUNPCKLPSY and VUNPCKLPDY and corresponding
> patterns. Once I added them everything started working.
>
> I found this all very confusing because it appears there are now two
> ways to match certain shuffle instructions in .td files: one through the
> traditional shuffle operators like unpc...