Displaying 12 results from an estimated 12 matches for "vtlist".
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2019 Jan 05
2
empty list assertion
Hi,
I'm trying to do a Debug build for the 1st time and I keep getting this assertion:
llvm-tblgen: CodeGenDAGPatterns.cpp:64: llvm::EEVT::TypeSet::TypeSet(llvm::ArrayRef<llvm::MVT::SimpleValueType>): Assertion `!VTList.empty() && "empty list?"' failed.
I do not know what list this assertion is referring to. Does anyone know? I always did Release builds before without any problem.
Thanks.
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2019 Jan 06
2
empty list assertion
...; wrote:
>
>> Hi,
>> I'm trying to do a Debug build for the 1st time and I keep getting this
>> assertion:
>>
>> llvm-tblgen: CodeGenDAGPatterns.cpp:64:
>> llvm::EEVT::TypeSet::TypeSet(llvm::ArrayRef<llvm::MVT::SimpleValueType>):
>> Assertion `!VTList.empty() && "empty list?"' failed.
>>
>> I do not know what list this assertion is referring to. Does anyone
>> know? I always did Release builds before without any problem.
>>
>> Thanks.
>> _______________________________________________
>...
2019 Jan 10
2
empty list assertion
...Hi,
> I'm trying to do a Debug build for the 1st time and I keep
> getting this assertion:
>
> llvm-tblgen: CodeGenDAGPatterns.cpp:64:
> llvm::EEVT::TypeSet::TypeSet(llvm::ArrayRef<llvm::MVT::SimpleValueType>):
> Assertion `!VTList.empty() && "empty list?"' failed.
>
> I do not know what list this assertion is referring to. Does
> anyone know? I always did Release builds before without any
> problem.
>
> Thanks.
> ____________________________...
2016 Mar 28
0
RFC: atomic operations on SI+
.../ "src comes from the first data-vgpr, cmp from the second."
> + SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, DL, ValVT, New, Cmp);
> +
> + SDValue Ops[] = {Swap->getChain(), Swap->getBasePtr(), Val};
> + ArrayRef<EVT> VTs = { MVT::v2i32, MVT::Other };
> + SDVTList VTList = { VTs.data(), VTs.size() };
> +
> + SDValue CmpSwap = DAG.getMemIntrinsicNode(AMDGPUISD::CMP_SWAP, DL, VTList,
> + Ops, MemVT, Swap->getMemOperand());
> + // TODO: What about ordering? synchscope?
> +
> + // Extract returne...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This
2009 Nov 13
1
[LLVMdev] legalize dag problem
thanks for the help ..I do add the chain and the result.
My code is like this ...
SDValue Ops[] = { load->getChain(), load->getOperand(1),
load->getBasePtr(), des };
DAG.getNode(CustomOpc, NodeTys, Ops, 4);
thanks again!
shrey
On Thu, Nov 12, 2009 at 4:41 PM, Anton Korobeynikov
<anton at korobeynikov.info> wrote:
>> My problem is that the second call asserts inside
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...LD(Op, SrcVT, Chain, StackSlot, DAG);
+}
+SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
+ SDValue StackSlot,
+ SelectionDAG &DAG) {
// Build the FILD
+ DebugLoc dl = Op.getDebugLoc();
SDVTList Tys;
bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
if (useSSE)
@@ -4792,36 +4802,54 @@
return SDValue();
return LowerUINT_TO_FP_i64(Op, DAG);
- } else if (SrcVT == MVT::i32) {
+ } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
return LowerUINT_TO_FP_i...
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...zationScope SynchScope);
/// getAtomic - Gets a node for an atomic op, produces result (if relevant)
@@ -726,9 +728,13 @@ public:
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes N operands.
SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,
- SDValue* Ops, unsigned NumOps, MachineMemOperand *MMO,
- AtomicOrdering Ordering,
+ SDValue *Ops, unsigned NumOps, MachineMemOperand *MMO,
+ AtomicOrdering SuccessOrdering,
+ AtomicOrdering Fail...
2014 Sep 19
2
[LLVMdev] More careful treatment of floating point exceptions
Hi Sanjay,
Thanks, I saw this flag and it's definitely should be considered, but
it appeared to me to be static characteristic of target platform. I'm
not sure how appropriate it would be to change its value from a front-end.
It says "Has", while optional flag would rather say "Uses" meaning that
implementation cares about floating point exceptions.
Regards,
Sergey
2014 Sep 25
2
[LLVMdev] More careful treatment of floating point exceptions
...bool exact);
+ /// Checks whether it's safe to replace floating point operation with it's
+ /// result. UnsafeOps is bit mask of unacceptable exceptions.
+ bool isSafeToOptimizeFPOp(APFloat::opStatus s,
+ APFloat::opStatus UnsafeOps) const;
+
/// VTList - List of non-single value types.
FoldingSet<SDVTListNode> VTListMap;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e2ead47..d5dd0eb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionD...