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Hi, The full trace stack: Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! [ 85%] Building X86GenEVEX2VEXTables.inc...  #0 0x000000000081b9b5 llvm::sys::PrintStackTrace(llvm::raw_ostream&) /home/nancy/work/rpp_clang/llvm/lib/Support/Unix...

You are welcome. I changed the pattern, the same old error pop up again, crash in the same place. Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri...

...p;gt; Subject: [EXT] Re:RE: [llvm-dev] Tablegen PAT limitation? &nbsp; Hi, &nbsp; The full trace stack: Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! [ 85%] Building X86GenEVEX2VEXTables.inc... &nbsp;#0 0x000000000081b9b5 llvm::sys::PrintStackTrace(llvm::raw_ostream&amp;) /home/nancy/work/rpp_cl...

...p;gt; Subject: [EXT] Re:RE: [llvm-dev] Tablegen PAT limitation? &nbsp; Hi, &nbsp; The full trace stack: Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! [ 85%] Building X86GenEVEX2VEXTables.inc... &nbsp;#0 0x000000000081b9b5 llvm::sys::PrintStackTrace(llvm::raw_ostream&amp;) /home/nancy/work/rpp_cl...

...empty before entering the loop ? > If TableGen crashes, it's a bug. Yes, it crashes. >> Casting intermediate i16 type results, I manage to generate instruction >> information but it throws another exception when generating the >> instruction selector :-(. >> >> vtInt: (vt:Other)<<P:Predicate_vtInt>> >> Type constraint application shouldn't fail! >> >> Looking again into the code, tblgen does not take into account the >> explicit casts when generating the instruction selector (RemoveAllTypes >> -> InferPossib...

...bnormal condition I shown. I presume this is a bug in tblgen, should not it verify that TypeVec is empty before entering the loop ? Casting intermediate i16 type results, I manage to generate instruction information but it throws another exception when generating the instruction selector :-(. vtInt: (vt:Other)<<P:Predicate_vtInt>> Type constraint application shouldn't fail! Looking again into the code, tblgen does not take into account the explicit casts when generating the instruction selector (RemoveAllTypes -> InferPossibleTypes) so it gets stuck earlier into the...

...hould not it verify that TypeVec is > empty before entering the loop ? If TableGen crashes, it's a bug. > Casting intermediate i16 type results, I manage to generate instruction > information but it throws another exception when generating the > instruction selector :-(. > > vtInt:     (vt:Other)<<P:Predicate_vtInt>> > Type constraint application shouldn't fail! > > Looking again into the code, tblgen does not take into account the > explicit casts when generating the instruction selector (RemoveAllTypes > -> InferPossibleTypes) so it gets s...

...ven just the backtrace from that would be very helpful. Thanks! Jim >>> Casting intermediate i16 type results, I manage to generate instruction >>> information but it throws another exception when generating the >>> instruction selector :-(. >>> >>> vtInt: (vt:Other)<<P:Predicate_vtInt>> >>> Type constraint application shouldn't fail! >>> >>> Looking again into the code, tblgen does not take into account the >>> explicit casts when generating the instruction selector (RemoveAllTypes >>&g...

...gt; If TableGen crashes, it's a bug. > > Yes, it crashes. > >>> Casting intermediate i16 type results, I manage to generate instruction >>> information but it throws another exception when generating the >>> instruction selector :-(. >>> >>> vtInt:     (vt:Other)<<P:Predicate_vtInt>> >>> Type constraint application shouldn't fail! >>> >>> Looking again into the code, tblgen does not take into account the >>> explicit casts when generating the instruction selector (RemoveAllTypes >>&gt...

..., it's a bug. >> Yes, it crashes. >> >>>> Casting intermediate i16 type results, I manage to generate instruction >>>> information but it throws another exception when generating the >>>> instruction selector :-(. >>>> >>>> vtInt: (vt:Other)<<P:Predicate_vtInt>> >>>> Type constraint application shouldn't fail! >>>> >>>> Looking again into the code, tblgen does not take into account the >>>> explicit casts when generating the instruction selector (RemoveAllT...

...t (i32 IntRegs:$dst), (mula_pat (v2i16 IntRegs:$a), (v2i16 IntRegs:$b)))]>; IntRegs is class with a type list of [i32, v2i16] But I get the following error when llvm building system try to generate the ISelector llvm[3]: Building Sparc.td DAG instruction selector implementation with tblgen vtInt: (vt:Other)<<P:Predicate_vtInt>> Type constraint application shouldn't fail!0 llvm-tblgen 0x081d6de7 1 llvm-tblgen 0x081d6b74 2 0x4001d400 __kernel_sigreturn + 0 3 libc.so.6 0x401b8a82 abort + 386 4 llvm-tblgen 0x0810a4ab 5 llvm-tblgen 0x0810a38f 6 llvm-tblg...