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...21/20 9:54 PM, Luo, Yuanke wrote: > > It seems I make a mistake on sharing register unit. Can we share > register unit for tile register that is within different tile register > class (different register class has different tile shape)?  Think > about two virtual tile register /%2:vtile1x1 /and /%3:vtile1x2/. First > %2 is allocated to $tmm0, after that %2 is killed and %t3 is allocated > to $tmm0. This is not allowed, because when $tmm0 is allocated to %2, > its shape is configured to 1x1. If we reallocated $tmm0 to %3, then we > need to re-config $tmm0 to 1x2 whi...

..., Luo, Yuanke wrote: > > It seems I make a mistake on sharing register unit. Can we share > register unit for tile register that is within different tile > register class (different register class has different tile > shape)?  Think about two virtual tile register /%2:vtile1x1 /and > /%3:vtile1x2/. First %2 is allocated to $tmm0, after that %2 is > killed and %t3 is allocated to $tmm0. This is not allowed, because > when $tmm0 is allocated to %2, its shape is configured to 1x1. If > we reallocated $tmm0 to %3, then we need to re-config $tmm...

...-helpful advice. -Hal On 8/21/20 9:54 PM, Luo, Yuanke wrote: It seems I make a mistake on sharing register unit. Can we share register unit for tile register that is within different tile register class (different register class has different tile shape)? Think about two virtual tile register %2:vtile1x1 and %3:vtile1x2. First %2 is allocated to $tmm0, after that %2 is killed and %t3 is allocated to $tmm0. This is not allowed, because when $tmm0 is allocated to %2, its shape is configured to 1x1. If we reallocated $tmm0 to %3, then we need to re-config $tmm0 to 1x2 which cause $tmm0~$tmm7 be clo...

Hi Hal, The proposal is attractive to me, but there is something I still can't figure out. Let's take below MIR as an example. We assume we have 256 register classes (vtile1x1, vtile1x2, ..., tile16x16). 1. After instruction selection, the pseudo AMX instruction is generated. The name of pseudo instructions have 'P' prefix. Now all the AMX pseudo instruction take vtile as register class. Let's assume %13 is constant 3, %10 is constant 4 and %14 is v...

The width and height can be runtime values that we would just copy into 64 byte configuration block we pass to ldtilecfg. So the code doesn't need to be multiversioned. The user code would also use those values to update pointers in the loops they write using the tiles. If we can't determine that two tiles were defined with the same width and height we need to assume the shape is different