search for: vtbit

...instead. All other values have similar > errors. Below is the current and proposed expansion in pseudo C++ for > all shift functions. Please let me know if I something is unclear. I'm not sure what you are saying, here is the code for shift-left. In the case of your example, Amt = 6, VTBits = 64 and NVTBits = 32. I've added comments at the end of various lines, like this: <== Comment. if (N->getOpcode() == ISD::SHL) { <== This branch is taken if (Amt > VTBits) { <== False ... not executed ... } else if (Amt > NVTBits) { <== False ... not execut...

Hi Duncan, The problem is the implementation of the expansion. Perhaps an example can help illustrate better. Take the case of a 64-bit integer shifted left by say 6 bits and is decomposed using 32-bit registers. Because 6 is less than the 32 (the register size) the resulting low part should be equal to the source low part shifted left by 6 bits. The current implementation places a zero

...ues have similar >> errors. Below is the current and proposed expansion in pseudo C++ for >> all shift functions. Please let me know if I something is unclear. > > I'm not sure what you are saying, here is the code for shift-left. In > the case of your example, Amt = 6, VTBits = 64 and NVTBits = 32. I've > added comments at the end of various lines, like this: <== Comment. > > if (N->getOpcode() == ISD::SHL) { <== This branch is taken > if (Amt > VTBits) { <== False > ... not executed ... > } else if (Amt > NVTBits)...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && - "This is not a shift!"); - - MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); - SDValue ShAmt = LegalizeOp(Amt); - MVT ShTy = ShAmt.getValueType(); - unsigned ShBits = ShTy.getSizeInBits(); - unsigned VTBits = Op.getValueType().getSizeInBits(); - unsigned NVTBits = NVT.getSizeInBits(); - - // Handle the case when Amt is an immediate. - if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { - unsigned Cst = CN->getZExtValue(); - // Expand the incoming operand to be shifte...