search for: vsx

Author: casper Repository: /hg/zfs-crypto/gate Revision: 24515d11f294677252853b5e1eb496c66b1e06e8 Log message: 6395215 UNIX03/UNIX98: *vsx* addition of mkstemps breaks namespace Files: update: usr/src/head/stdlib.h

Author: aj Repository: /hg/zfs-crypto/gate Revision: 7567fbd5fb7e1615c352bd1e1f9cdeba24d5e961 Log message: 6406622 UNIX98/UNIX03: *vsx* Trusted Extensions changes to tar.h pollute standards namespace Files: update: usr/src/head/tar.h

Anyone have any experience tying the Polycom VSX 7000e & Asterisk together? It says it supports standards based SIP servers but thought I'd see if anyone had real world experience. Thanks, Ken -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.digium.com/pipermail/asterisk-users/attachments/200...

I'm looking to buy a new workstation, and it looks like Thinkmate makes what I need -- their vsx "virtually silent" variety. I hestitate because I wasn't happy with a laptop I bought a few years ago from a small outfit that sold Linux boxes exclusively. Does anyone have experience with Thinkmate, and in particular, the VSX line? If the later, is it really quiet. I run Centos o...

Hi people, Unlike GCC, LLVM has seemingly good support for interoperability with MSVC built windows code. This makes LLVM particularly attractive to my company/project, but it seems LLVM doesn't support writing PDB debug into into it's COFF output. It seems Win64 exception handling has been added recently, which perhaps makes PDB the only outstanding feature for effective use with

I was wondering if anyone can help me with a problem we have at one of our sites. We have setup a Asterisk Trunk to a Avaya PBX, ie ... Avaya <-> Asterisk (1.2.30) <-> External ISDN Network BUT They also have a Polycom VSX 7000 that with some sort of BRI converters that plugs into the Avaya. The Trunk is working well except for Video Conference Calls. The Polocom can receive but not make calls, and the calls that it receives drop out every 5 minutes. Short of telling them to fork out for a BRI service does anyone h...

...the inspiration to create a DWARF debug module for >>> visual studio, then quickly go lost trying to get started. It looks like >>> google has/is attempting to go down this road according to the pages: >>> >>> >>> http://www.chromium.org/nativeclient/sdk/vsx-plugin/vsx-reference-material >>> http://code.google.com/p/nativeclient/wiki/NaClDebugging >>> >>> though a more recent page doesn't mention visual studio: >>> >>> https://developers.google.com/native-client/devguide/devcycle/debugging >>> &...

Hello, Has anyone used Polycom's VSX line of videoconferencing equipment with Asterisk? It seems some of their models, namely the newer VSX 5000, supports SIP. -- The Internet used to be a lot of smart people sitting at dumb terminals, but now its a lot of dumb people sitting at smart terminals!

...descriptor. Targets supporting this that I know of are all bare-metal (so powerpc-none-elf). I'm trying to implement ELF support right now. VLE ELF files should have a section header flag set (SHF_PPC_VLE = 0x10000000). I have added a subtarget feature "vle", similar to Altivec, SPE, VSX etc and I'm enabling this feature for appropriate CPUs. Now, functions that are compiled with "vle" feature should go into a different text section (text_vle). I can see that TargetMachine has a method getSubtargetImpl which can be overridden for the implementation and it can return...

...75, ttl=3600) Name=PopCon, Records=1, Children=0 A: 192.168.0.24 (flags=f0, serial=27217, ttl=1200) Name=tux, Records=1, Children=0 A: 192.168.0.10 (flags=f0, serial=18525, ttl=900) Name=TX-8050, Records=1, Children=0 A: 192.168.0.13 (flags=f0, serial=7047, ttl=3600) Name=VSX-1021, Records=1, Children=0 A: 192.168.0.12 (flags=f0, serial=7046, ttl=3600) Regards Timmi

...y Yes. The memory pattern differs. This is the first diagram on the right at: http://llvm.org/docs/BigEndianNEON.html#bitconverts ) I think that teaching the optimizer about big-Endian lane ordering would have been better. Inserting the REV after every LDR sounds very similar to what we do for VSX on little-Endian PowerPC systems (PowerPC may have a slight advantage here in that we don't need to do insertelement / extractelement / shufflevector through memory on systems where little-Endian mode is relevant, see http://llvm.org/devmtg/2014-10/Slides/Schmidt-SupportingVectorProgramming.pdf...

...adds initial vector support for PowerPC64. On POWER9, flac --best is about 3.3x faster. Amitay Isaacs (2): Add m4 macro to check for C __attribute__ features Check if compiler supports target attribute on ppc64 Anton Blanchard (5): configure.ac: Remove SPE detection code configure.ac: Add VSX enable/disable configure.ac: Fix FLAC__CPU_PPC on little endian, and add FLAC__CPU_PPC64 Add runtime detection of POWER8 and POWER9 Add VSX optimised versions of autocorrelation loops configure.ac | 53 +- m4/c_attribute.m4 | 18 + src/libFLAC/Make...

...iffers. This is the first diagram on the > right at: http://llvm.org/docs/BigEndianNEON.html#bitconverts ) > > > I think that teaching the optimizer about big-Endian lane ordering > would have been better. Inserting the REV after every LDR sounds > very similar to what we do for VSX on little-Endian PowerPC systems > (PowerPC may have a slight advantage here in that we don't need to > do insertelement / extractelement / shufflevector through memory on > systems where little-Endian mode is relevant, see > http://llvm.org/devmtg/2014-10/Slides/Schmidt-SupportingV...

...finition of LBZU and friends in lib/Target/PowerPC/PPCInstrInfo.td. > For a simpler example of just the `RegConstraint` usage (as it doesn't use a compound > node like PPC's address nodes), you can look at all the fused multiply-add such as > XSMADDADP in lib/Target/PowerPC/PPCInstrVSX.td. > > Hope this helps. Thanks! However, none of the NoEncode examples in PPCInstrInfo.td seem to have an isel pattern; and the VSX examples, like XSMADDADP, seem to match on setting a single output: let BaseName = "XSMADDADP" in { let isCommutable = 1 in def XSMADDA...

...or support? (b) The situation you describe isn't the one that applies to llvmpipe. In llvmpipe the vectors are nice, known widths that are under the driver's own control. We certainly don't want to scalarise and revectorise llvmpipe IR on x86_64, or on powerpc with Altivec/VSX. The original code is already well vectorised for those targets. (And also for ARM NEON I expect.) In the llvmpipe case, codegen's type legaliser already makes a good decision about what to scalarise and what not to scalarise, without any help from llvmpipe. The problem I&...

How does this make any sense? NEON intrinsics are there to support code generation targeting the ARM NEON SIMD unit on the ARM architecture. Power/PowerPC as it's own AltiVec/VSX SIMD units, which in turn has it's own intrinsics. If you want write code that explicitly targets CPU execution units it's necessarily tied to that specific CPU architecture. If you just want to test code for written for a different CPU on a development box your best bet is to use a VM li...

...6 (flags=f0, serial=1567 5, ttl=3 600) Name=PopCon, Records=1, Children=0 A: 192.168.0.24 (flags=f0, serial=27217, ttl=1200) Name=tux, Records=1, Children=0 A: 192.168.0.10 (flags=f0, serial=18525, ttl=900) Name=TX-8050, Records=1, Children=0 A: 192.168.0.13 (flags=f0, serial=7047, ttl=3600) Name=VSX-1021, Records=1, Children=0 A: 192.168.0.12 (flags=f0, serial=7046, ttl=3600) root at DRAGO:~# Regards Michael Am 2020-11-17 15:20, Mani Wieser via samba <samba at lists.samba.org> schrieb: > > Dear Michael > > How have you created the subdomain? > > to look it up you have t...

...one into which to > transfer the condition register's contents). I'd like to improve > this at some point. I forgot to add: - Altivec support currently seems broken (there are some tests with altivec intrinsics in the test suite, these all fail to compile) - There is no VSX support. -Hal > > So if you stick to static linking and don't use TLS or long doubles, > then it actually works quite well. Dynamic linking on PPC64 works most > of the time. I've tried to keep the PPC 970 hazard detector in working > order, but I've never really done...

...(b) The situation you describe isn't the one that applies to llvmpipe. > In llvmpipe the vectors are nice, known widths that are under the > driver's own control. We certainly don't want to scalarise and > revectorise llvmpipe IR on x86_64, or on powerpc with Altivec/VSX. > The original code is already well vectorised for those targets. > (And also for ARM NEON I expect.) > > In the llvmpipe case, codegen's type legaliser already makes a good > decision about what to scalarise and what not to scalarise, without > any help from...

Hello Hal, I am not very familiar with the DSP capabilities of PowerPC, but I imagine there will be instructions for simple vector operations like vector addition, multiplication, etc. so for these I imagine the implementation would consist of just outputting the correct instruction. However, for NEON instructions like the reciprocal step (see