search for: vsldoi

...nto v0-v7 and initial history into v8-v15 li r31,0xf and r31,r8,r31 ; r31: data%4 li r11,16 subf r31,r31,r11 ; r31: 4-(data%4) slwi r31,r31,3 ; convert to bits for vsro li r10,-4 stw r31,-4(r9) lvewx v0,r10,r9 vspltisb v18,-1 vsro v18,v18,v0 ; v18: mask vector li r31,0x8 lvsl v0,0,r31 vsldoi v0,v0,v0,12 li r31,0xc lvsl v1,0,r31 vspltisb v2,0 vspltisb v3,-1 vmrglw v2,v2,v3 vsel v0,v1,v0,v2 ; v0: reversal permutation vector add r10,r5,r6 lvsl v17,0,r5 ; v17: coefficient alignment permutation vector vperm v17,v17,v17,v0 ; v17: reversal coefficient alignment permutation vector...

Sadly the latest optimization broke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register)

...line: `(0xfffffc00)' lpc_asm.s:85: Error: Unrecognized opcode: `lvewx' lpc_asm.s:86: Error: Unrecognized opcode: `vspltisb' lpc_asm.s:87: Error: Unrecognized opcode: `vsro' lpc_asm.s:90: Error: Unrecognized opcode: `lvsl' lpc_asm.s:91: Error: Unrecognized opcode: `vsldoi' lpc_asm.s:93: Error: Unrecognized opcode: `lvsl' lpc_asm.s:94: Error: Unrecognized opcode: `vspltisb' lpc_asm.s:95: Error: Unrecognized opcode: `vspltisb' lpc_asm.s:96: Error: Unrecognized opcode: `vmrglw' <snip> At least some of those error look like Alti...

On 7/2/2018 3:16 PM, Sanjay Patel wrote: > I also agree that the per-element rotate for vectors is what we want for > this intrinsic. > > So I have this so far: > > declare i32 @llvm.catshift.i32(i32 %a, i32 %b, i32 %shift_amount) > declare <2 x i32> @llvm.catshift.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %shift_amount) > > For