search for: vs_32

Hi Tom, The output: Added VReg_64(explicit) Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) is saying that VS_32 was added because VReg_64 was explicitly specified and that while inspecting VS_32, it noticed that every register in VS_32 was a subregister of a register from VReg_64 using a single common subregister index. I've adde...

Hi, I've run into an issue with the RegisterBankEmitter on the AMDGPU backend. AMDGPU has a register class: VS_32, which is non-allocatable and contains registers from both defined register banks (SGPRRegBank and VGPRRegBank). The RegisterBankEmitter is adding this class to the CoverageData array for both register classes, because it contains sub-registers of one of the classes explicitly added to the Registe...

...lass because they are both called sub0 ? -Tom >> On 10 May 2017, at 21:58, Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi Tom, >> >> The output: >> Added VReg_64(explicit) >> Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) >> is saying that VS_32 was added because VReg_64 was explicitly specified and that while inspecting VS_32, it noticed that every register in VS_32 was a subregister of a register from VReg_64 using a single common subregister index. >&...

...load unit that can hold up to 31 loads waiting to be executed, but only 1 load can be executed at a time. Pick Top CLUSTER Scheduling SU(43) %vreg46<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 48; mem:LD4[<unknown>] SGPR_32:%vreg46 SReg_128:%vreg9 SReg_32: 45 > 44(+ 0 livethru) VS_32: 51 > 18(+ 0 livethru) Ready @46c HWLGKM +1x105u TopQ.A BotLatency SU(43) 78c *** Max MOps 1 at cycle 46 Cycle: 47 TopQ.A TopQ.A @47c Retired: 47 Executed: 47c Critical: 47c, 47 MOps ExpectedLatency: 10c - Latency limited. BotQ.A RemLatency SU(1698) 99c TopQ.A + Remain MOps:...

Hi, I have a program with over 100 loads (each with a 10 cycle latency) at the beginning of the program, and I can't figure out how to get the machine scheduler to intermix ALU instructions with the loads to effectively hide the latency. It seems the issue is with load clustering. I restrict load clustering to 4 at a time, but when I look at the debug output, the loads are always being