Displaying 3 results from an estimated 3 matches for "vrf128".
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vr128
2016 Mar 10
2
Greedy register allocator allocates live sub-register
Hi all,
I've come across a problem with register allocation which I have been
unable to track down the root cause of.
6728B %vreg304<def> = COPY %vreg278; VRF128:%vreg304,%vreg278
6736B %vreg302<def> = COPY %vreg278; VRF128:%vreg302,%vreg278
6752B %vreg278<def,tied1> = foo %vreg278<tied0>, %vreg277, 14, pred:1,
pred:%noreg, 5; VRF128:%vreg278 VRF64_l:%vreg277
* bar 30, %vreg278; VRF128:%vreg278
6760B %vreg302<def,tied1> = foo %vreg3...
2016 May 18
3
sum elements in the vector
...not a pattern fragment). For example, for AND, ADD (horizontal sum), OR and XOR of 4 elements we use something like the following TableGen structure:
class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType vt, string asmstr> :
SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),
!strconcat(asmstr, " $dst $src"),
[(set regVT:$dst,
(opc (rt (vector_extract(vt VRF128:$src), 0 ) ),
(opc (rt (vector_extract(vt VRF128:$src), 1 ) ),
(opc (rt (vecto...
2016 May 16
4
sum elements in the vector
This would be really cool. We have several instructions that perform horizontal vector operations, and have to use built-ins to select them as there is no easy way of expressing them in a TD file. Some like SUM for a ‘v4i32’ are easy enough to express with a pattern fragment, SUM ‘v8i16’ takes TableGen a long time to compute, but SUM ‘v16i8’ resulted in TableGen disappearing into itself for