search for: vreg59

...] 832 %vreg57:lo16<def> = mv_any16 0; aN40_0_7:%vreg57 So both REG_SEQUENCE and the temporary vreg1 have been removed, and a1_gh is written directly at the right place in vreg57 in the function entry and the l part of vreg57 is written much later. During register allocation a new temporary vreg59 seems to be introduced for some part of vreg57 and we get 16L %vreg59:hi24<def,undef> = COPY %a1_gh<kill>, %vreg59<imp-def>; aN40_0_7:%vreg59 Due to high register pressure vreg59 is spilled **** Local spiller rewriting MBB '': %vreg59:hi24<def,undef> = COPY %a1...

...imp-def>, ... ADJCALLSTACKUP 0, 0, %SP<imp-def>, %EX<imp-def>, %SP<imp-use> %vreg57<def> = COPY %A<kill>; GR16:%vreg57 %vreg58<def> = SUB16rr %vreg57, %vreg18<kill>, %EX<imp-def>; GR16:%vreg58,%vreg57 GEXR16:%vreg18 %vreg59<def> = ADD16rm %vreg58<kill>, <fi#1>, 16, %EX<imp-def>; mem:LD1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59,%vreg58 MOV16mr <fi#1>, 16, %vreg59; mem:ST1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59 %vreg20<def> = COPY %v...

...st one iteration away, and the uses appear before the definition, then the copies should be coalesced away. In the examples that you show below, it all depends in which iteration each instruction is scheduled and/or the order in which the instructions are scheduled. %vreg73<def> = PHI %vreg59, <BB#5>, %vreg62, <BB#6>; %vreg61<def> = INSN1 %vreg1, %vreg73; %vreg62<def> = INSN2 %vreg73, %vreg5; %vreg64<def> = INSN1 %vreg2, %vreg73; For some reason, the instruction defining vreg64 was scheduled after the instruction defining vreg62, which causes t...

Hi - I replied to the original sender only by mistake. Sorry about that. When we started working on the pipeliner, and added it before the scheduler, we also were concerned that the scheduler or other passes would undo the work of the pipeliner. The initial thought was that we would add information (using metadata or some other way like you've suggested) to the basic block to tell the

Hi, I have some questions about the implementation of Software pipeline in MachinePipeliner.cpp. First, in hexagon backend, between MachinePipeliner and regalloc pass, there're some other passes like phi eliminate, two-address, register coalescing, which may change or insert intructions like 'copy' in MBB, and swp kernel loop may be destroyed by these passes. Why not put