Displaying 3 results from an estimated 3 matches for "vreg56".
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2013 Jan 14
2
[LLVMdev] Splitting live ranges of half-defined registers
...vreg'(32).high_half (2)
When this happens, the assignment (2) basically reads an undefined register.
A scenario like this happens in real life. Look at vreg304 below:
BB#2: derived from LLVM BB %if.end
Predecessors according to CFG: BB#1
%vreg61<def> = LDrih_indexed %vreg56, 3134; IntRegs:%vreg61,%vreg56
%vreg62<def> = LDriuh_indexed %vreg56, 680; IntRegs:%vreg62,%vreg56
%R1<def> = TFRI 1431655766
ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>,
%R31<imp-use>, %R30<imp-use>, %R29<imp-use>...
2012 Jan 05
0
[LLVMdev] Spilling of partly (un)defined registers
...n
the g and h part of a register.
# *** IR Dump Before Linear Scan Register Allocator ***:
# Machine code for function accumconv:
Function Live Ins: %a0_gh in %vreg0, %a1_gh in %vreg1
BB#0: derived from LLVM BB %0
Live Ins: %a0_gh %a1_gh
%vreg1<def> = COPY %a1_gh; aNgh_0_7:%vreg1
[...]
%vreg56<def> = mv_any16 0; aNl_0_7:%vreg56
%vreg57<def> = REG_SEQUENCE %vreg1, hi24, %vreg56, lo16;
aN40_0_7:%vreg57 aNgh_0_7:%vreg1 aNl_0_7:%vreg56
So the in-argument in a1_gh is saved in vreg1, and used later in a
REG_SEQUENCE instruction to write a full register, vreg57.
After the REG_SE...
2013 Oct 09
4
[LLVMdev] Subregister liveness tracking
On Oct 8, 2013, at 2:06 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> What I didn't mention in r192119 is that mthi/lo clobbers the other sub-register only if the contents of hi and lo are produced by mult or other arithmetic instructions (div, madd, etc.) It doesn't have this side-effect if it is produced by another mthi/lo. So I don't think making mthi/lo clobber the