search for: vreg50

...stom Instruction selection for BUILD_VECTOR, which gets converted in my back end's machine instrution VLOAD_D, although the custom code seems to always select instructions in a valid way.) ******** Pre-regalloc Machine LICM: Test ******** Entering BB#4 Hoist non-reg-pressure: %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16 Hoisting %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16 from BB#4 to BB#3 Hoist non-reg-pressure: %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51 Hoisting %vreg51<def> = VLOAD_D 0; MS...

...register coalescing decisions (CoalescerPair::Partial = 0). For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50, the "parent" super reg. Is there a way to work around this? It causes unnecessary copies. Thanks, Joe -------------- next part -------------- An HTML attachment was scrubbed... URL: <h...

...oalescing decisions (CoalescerPair::Partial = 0). > > For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50, the "parent" super reg. > > Is there a way to work around this? It causes unnecessary copies. Is this happening on trunk, or are you using an old version of LLVM? /jakob

...d read-undef does not convey the right information for the > subsequent uses of Reg5. > > You can give it a try and see how it goes. I tried setting isUndef to trie when handling INSERT_SUBREG in TwoAddressInstructioPass.cpp, but then I run into stuff like this instead: 832B %vreg50:hi16<def,read-undef> = COPY %vreg0 848B ... 864B %vreg19<def,dead> = COPY %vreg50 880B %vreg19:lo16<def,read-undef> = COPY %vreg73 896B ... 912B mv_a32_r16_rmod1 %vreg19, %vreg20 ... *** Bad machine code: Multiple connected...

...lescerPair::Partial = 0). > > > > For example, I have a super reg that has r20, r21, r22, and r23 physical > registers. This super reg is the dest of a reg_sequence which generates 4 > COPY MIs. The first COPY coalesces (merging into r20), but the vregs for > r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that > because doing so generates inteference on %vreg50, the "parent" super reg. > > > > Is there a way to work around this? It causes unnecessary copies. > > Is this happening on trunk, or are you using an old version of L...

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,

...: 1104r%vreg47<def,dead> = COPY %vreg27:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg27 Shrunk: [400r,400d:0)[1104r,1104d:2)  0 at 400r 1 at x 2 at 1104r 2 components: [400r,400d:0)[1104r,1104d:1)  0 at 400r 1 at 1104r [400r,400d:0)  0 at 400r [1104r,1104d:0)  0 at 1104r Deleting dead def 1104r%vreg50<def,dead> = COPY %vreg27:sel_z; R600_Reg32:%vreg50 R600_Reg128:%vreg27 Deleting dead def 400r%vreg47<def,dead> = COPY %C1_Y; R600_Reg32:%vreg47 Shrink: [128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi...

...= COPY %vreg27:sel_z; > R600_Reg32:%vreg47 R600_Reg128:%vreg27 > Shrunk: [400r,400d:0)[1104r,1104d:2)  0 at 400r 1 at x 2 at 1104r > 2 components: [400r,400d:0)[1104r,1104d:1)  0 at 400r 1 at 1104r > [400r,400d:0)  0 at 400r > [1104r,1104d:0)  0 at 1104r > Deleting dead def 1104r%vreg50<def,dead> = COPY %vreg27:sel_z; > R600_Reg32:%vreg50 R600_Reg128:%vreg27 > Deleting dead def 400r%vreg47<def,dead> = COPY %C1_Y; R600_Reg32:%vreg47 > Shrink: > [128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4) >  0 at 128r 1 at 192r 2 at 2...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2