Displaying 20 results from an estimated 26 matches for "vreg31".
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2015 Oct 13
2
MachineSink optimization in code containing a setjmp
...struction into a following machine basic block (not necessarily a
successor), even when that later block can be reached through a setjmp.
Here is some example debug output from llc that I'm seeing:
Sinking along critical edge.
Sink instr %vreg8<def,tied1> = ADD64rr %vreg14<tied0>, %vreg31,
%EFLAGS<imp-def,dead>; GR64:%vreg8,%vreg14,%vreg31
into block BB#11:
Predecessors according to CFG: BB#8 BB#10 BB#32
...
EH_SjLj_Setup <BB#36>, <regmask>
Successors according to CFG: BB#34 BB#36
Sinking along critical edge.
Sink instr %vreg8<def,tied1&...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<&l...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...t0, Register:i64 %vreg23, t1
t11: v8i64 = VLOAD_D TargetConstant:i64<0>
t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11
t8: ch = TokenFactor t3, t6
t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8
[...]
Spilling live registers at end of block.
Spilling %vreg31 in %R0 to stack slot #5
Spilling %vreg32 in %Wd0 to stack slot #6
BB#3: derived from LLVM BB %vector.body.preheader
Predecessors according to CFG: BB#2
%Wd0<def> = VLOAD_D 0
%R0<def> = MOV_ri 0
STD %R0<kill>, <fi#5>, 0
STD %Wd0<kil...
2012 Jul 06
0
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
...consider this code (part of a single block loop).
MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30,
2, // Post Inc. Load. Vreg7 is a 64bit reg.
MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill>
// This is the A3 = B0 above.
MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill>
// Use the lo subreg that was setup in MI1:
....
....
MI4:: %vreg32<def> = COPY %vreg7; //Not trivial
because 7 is not killed. This is the Copy C i.e. B1=A3.
....
MI5:: Conditional jump back...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...0; R600_Reg32:%vreg29,%vreg0,%vreg7
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
// LOOP BODY
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
944B%vreg35<def> = COPY %vreg32<...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote:
> The code in collectRanges() does:
>
> // Collect ranges for register units. These live ranges are computed on
> // demand, so just skip any that haven't been computed yet.
> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
> for (MCRegUnitIterator Units(Reg,
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...g7
> 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%noreg
>
> // LOOP BODY
> 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
> 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
> 944B%vreg35<def> =...
2012 Jul 05
3
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi Jakob,
Thanks for your reply.
>
> The <undef> flag goes on NewMI_1 because the virtual register B isn't live
> before that instruction.
>
> But you probably shouldn't be doing this yourself. Your NewMI code isn't
in
> SSA form because B has multiple definitions. Just use a REG_SEQUENCE
> instruction, and let the register allocator do the transformation
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<&l...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13<def> = BDNZ8 %vreg13,
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
The code in collectRanges() does:
// Collect ranges for register units. These live ranges are computed on
// demand, so just skip any that haven't been computed yet.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...ived from LLVM BB %entry
>> Live Ins: %R0 %R1 %D1 %D2
>> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
>> 12B %vreg30<def> = LDriw <fi#-1>, 0;
>> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
>> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
>> IntRegs:%vreg31
>> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
>> 28B %vreg106<def> = TFRI 16777216;
>> IntRegs:%vreg106<<<<<<<<<<<<...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...ill>
Successors according to CFG: BB#8 BB#10
the preheader is:
240B BB#3:
Predecessors according to CFG: BB#2
256B %vreg28<def> = LI 0; GPRC:%vreg28
272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17
288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30
304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31
320B B <BB#8>
Successors according to CFG: BB#8
So maybe LiveInterval would need to be updated to support terminators...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...11: v8i64 = VLOAD_D TargetConstant:i64<0>
> t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11
> t8: ch = TokenFactor t3, t6
> t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8
>
> [...]
>
> Spilling live registers at end of block.
> Spilling %vreg31 in %R0 to stack slot #5
> Spilling %vreg32 in %Wd0 to stack slot #6
> BB#3: derived from LLVM BB %vector.body.preheader
> Predecessors according to CFG: BB#2
> %Wd0<def> = VLOAD_D 0
> %R0<def> = MOV_ri 0
> STD %R0<kill>, <fi#5&g...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...= COPY %vreg46<kill>; R600_Reg32:%vreg46
864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
BB#3:# derived from
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
register: %vreg31 +[896r,912r:0)
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
register: %vreg32 +[912r,944r:0)
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...; R600_Reg32:%vreg46
> 864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>,
> %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>,
> %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
> BB#3:# derived from
> 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31
> R600_Reg128:%vreg6
> register: %vreg31 +[896r,912r:0)
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>;
> R600_Reg128:%vreg32 R600_Reg32:%vreg31
> register: %vreg32 +[912r,944r:0)
> 928B%vreg34<def> =...