search for: vreg30

...;kill>; R600_Reg32:%vreg47,%vreg2 %vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3 %vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13     Successors according to CFG: BB#1 BB#1: derived from LLVM BB %25     Predecessors according to CFG: BB#0 BB#3 %vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg0,%vreg49 %PREDICATE_BIT<def> = PRED_X %vreg30, 152, 16; R600_Reg32:%vreg30 JUMP <BB#3>, pred:%PREDICATE_BIT JUMP <BB#2>, pred:%noreg     Successors accord...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...> %vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3 > %vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13 > Successors according to CFG: BB#1 > > BB#1: derived from LLVM BB %25 > Predecessors according to CFG: BB#0 BB#3 > %vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg0,%vreg49 > %PREDICATE_BIT<def> = PRED_X %vreg30, 152, 16; R600_Reg32:%vreg30 > JUMP <BB#3>, pred:%PREDICATE_BIT > JUMP <BB#2>, pred:%noreg >...

...%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30 560BJUMP <BB#3>, pred:%PREDICATE_BIT 576BJUMP <BB#2>, pred:%noreg // LOOP BODY 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg3...

...t; = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48 > 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49 > 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 > 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 > 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30 > 560BJUMP <BB#3>, pred:%PREDICATE_BIT > 576BJUMP <BB#2>, pred:%noreg > > // LOOP BODY > 896B%vreg31<def> =...

...r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)... I schedule the following instruction (48B): 0B BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<&...

...g7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49 register: %vreg7 +[496r,592B:0) +[880B,1088r:0) 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 register: %vreg29 +[512r,528r:0) 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 register: %vreg30 +[528r,544r:0) 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30 560BJUMP <BB#3>, pred:%PREDICATE_BIT 576BJUMP <BB#2>, pred:%noreg BB#2:# derived from  608B%vreg39&l...

...,416r:4)... > R5 = [0B,32r:0)[400r,416r:4)... > > I schedule the following instruction (48B): > > 0B BB#0: derived from LLVM BB %entry > Live Ins: %R0 %R1 %D1 %D2 > 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B...

...49<kill>; R600_Reg32:%vreg7,%vreg49 > register: %vreg7 +[496r,592B:0) +[880B,1088r:0) > 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, > 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 > register: %vreg29 +[512r,528r:0) > 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 > register: %vreg30 +[528r,544r:0) > 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; > R600_Reg32:%vreg30 > 560BJUMP <BB#3>, pred:%PREDICATE_BIT > 576BJUMP <BB#2>, pred:%noreg > BB#...

..... B1 = A3 <--The copy C And if so, we check if we can merge the two ranges of B into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill> // Use the lo subreg th...

...)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)... I schedule the following instruction (48B): 0B BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFR...

On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote: > The code in collectRanges() does: > > // Collect ranges for register units. These live ranges are computed on > // demand, so just skip any that haven't been computed yet. > if (TargetRegisterInfo::isPhysicalRegister(Reg)) { > for (MCRegUnitIterator Units(Reg,

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

...before and after PHI nodes elimination. 1. Before PHI nodes elimination. -Machine IR: BB#14: derived from LLVM BB %for.cond151.preheader Predecessors according to CFG: BB#12 BB#13 %vreg29<def> = PHI %vreg25, <BB#12>, %vreg28, <BB#13>; CPURegs:%vreg29,%vreg25,%vreg28 %vreg30<def> = PHI %vreg26, <BB#12>, %vreg27, <BB#13>; CPURegs:%vreg30,%vreg26,%vreg27 BNE %vreg81<kill>, %ZERO, <BB#17>; CPURegs:%vreg81 J <BB#15> Successors according to CFG: BB#15 BB#17 BB#15: derived from LLVM BB %for.body156.preheader Predecessors a...

...r:5)... > R4 = [0B,32r:0)[384r,416r:4)... > R5 = [0B,32r:0)[400r,416r:4)... > > I schedule the following instruction (48B): > > 0B BB#0: derived from LLVM BB %entry > Live Ins: %R0 %R1 %D1 %D2 > 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 167772...

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

The code in collectRanges() does: // Collect ranges for register units. These live ranges are computed on // demand, so just skip any that haven't been computed yet. if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))

...)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)... I schedule the following instruction (48B): 0B BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFR...

...= [0B,32r:0)[400r,416r:4)... >> >> I schedule the following instruction (48B): >> >> 0B BB#0: derived from LLVM BB %entry >> Live Ins: %R0 %R1 %D1 %D2 >> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 >> 12B %vreg30<def> = LDriw <fi#-1>, 0; >> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] >> IntRegs:%vreg31 >> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 >>...

On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote: > > I've described that issue (see below) when you were out of town... I think > I am getting more context on it. Please take a look... > > So, in short, when the new MI scheduler performs move of an instruction, it > does something like this: > > // Move the instruction to its new