Displaying 4 results from an estimated 4 matches for "vreg2sunitmap".
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...transitively redundant with antidependencies from this definition's
// uses. We're conservative for now until we have a way to guarantee the
uses
// are not eliminated sometime during scheduling. The output dependence
edge
// is also useful if output latency exceeds def-use latency.
VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
if (DefI == VRegDefs.end())
VRegDefs.insert(VReg2SUnit(Reg, SU));
else {
SUnit *DefSU = DefI->SU;
if (DefSU != SU && DefSU != &ExitSU) {
unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...oint:
>
> VRegDefs.insert(VReg2SUnit(Reg, SU));
>
> But later, when checking for anti dependency for another MI here:
>
> void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
> ...
> // Add antidependence to the following def of the vreg it uses.
> VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
> if (DefI != VRegDefs.end() && DefI->SU != SU)
> DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
>
> We will never find that def in VRegDefs.find(Reg) even though it exists.
>
> I know this has been working for a while,...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
Andy,
Thanks for reply. I was able to trace the problem to the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...d())
return;
we do not ever get to this point:
VRegDefs.insert(VReg2SUnit(Reg, SU));
But later, when checking for anti dependency for another MI here:
void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
...
// Add antidependence to the following def of the vreg it uses.
VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
if (DefI != VRegDefs.end() && DefI->SU != SU)
DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
We will never find that def in VRegDefs.find(Reg) even though it exists.
I know this has been working for a while, but I am still missing someth...