search for: vreg19

Hi, I am debugging private backend and faced interesting problem: sometimes spill hoisting creates double stores. (some output from -debug-only=regalloc). First hoisting: Checking redundant spills for 0 at 16r in %vreg19 [16r,144B:0)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5) 0 at 16r 1 at 144B-phi 2 at 240B-phi 3 at 296r 4 at 416B-phi 5 at 472r Merged to stack int: SS#0 [16r,592B:0) 0 at x hoisted: 16r STbo %vreg19, <fi#0> Second below: Checking redundant spills for 0 at 16r in %...

...g5. > > You can give it a try and see how it goes. I tried setting isUndef to trie when handling INSERT_SUBREG in TwoAddressInstructioPass.cpp, but then I run into stuff like this instead: 832B %vreg50:hi16<def,read-undef> = COPY %vreg0 848B ... 864B %vreg19<def,dead> = COPY %vreg50 880B %vreg19:lo16<def,read-undef> = COPY %vreg73 896B ... 912B mv_a32_r16_rmod1 %vreg19, %vreg20 ... *** Bad machine code: Multiple connected components in live interval *** - function: fixedconv - interval: %vreg19 [864r...

...Live Ins: %T1_X %T1_Y %T1_Z %T1_W %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 %vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 %vreg23<def> = COPY %vreg19<kill>; R60...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...T1_W > %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 > %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 > %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 > %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 > %vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 > %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 > %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 > %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 > %vreg23<def> = COPY %vreg19&l...

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,

...8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1 424B %vreg4<def> = DIVD %vreg2, %vreg3; G8RC:%vreg4,%vreg2,%...

...T1_W; R600_TReg32:%vreg17 %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18 %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20 %vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14 %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2 %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22 %vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg...

...%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 > %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 > %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 > %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18 > %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20 > %vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14 > %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2 > %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22 > %vreg21<def,tied1> = INSERT_SUBREG %vreg22<t...

...r,240r:0) 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 register: %vreg15 +[48r,160r:0) 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14 register: %vreg14 +[64r,96r:0) 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 register: %vreg18 +[80r,128r:0) 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 register: %vreg19 +[96r,144r:0) 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 register: %vreg2 +[112r,400r:0) 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg...

...; = COPY %T1_Y<kill>; R600_TReg32:%vreg15 > register: %vreg15 +[48r,160r:0) > 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14 > register: %vreg14 +[64r,96r:0) > 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 > register: %vreg18 +[80r,128r:0) > 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; > R600_Reg128:%vreg19 R600_TReg32:%vreg14 > register: %vreg19 +[96r,144r:0) > 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 > register: %vreg2 +[112r,400r:0) > 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<k...

...e to false predicate) at index 162, continuing at 236 Match failed at index 241 Continuing at 263 LLVM ERROR: Cannot select: t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64 t6: v8i64,ch = CopyFromReg t0, Register:v8i64 %vreg19 t5: v8i64 = Register %vreg19 t171: i64 = FrameIndex<6> t73: i64 = undef In function: foo I actually have difficulties in understanding in the Selection DAG what the FixedStack operand means. Also, it is not really clear for me how to handle i...

...1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112 %vreg190<def> = MOVSDrm <fi#0>, 1, %noreg, 120, %noreg; mem:LD8[%85] FR64:%vreg190 %vreg191<def> = MOVSDrm <fi#0>, 1, %noreg, 96, %noreg; mem:LD8[%87] FR64:%vreg191 %vreg192<def> = MOVSDrm <fi#0>, 1, %noreg, 88, %noreg; mem:LD8[%92] FR64:%vreg192 %vreg193<def> =...

..._NOX0:%vreg1 >> 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 >> 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 >> 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 >> 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1 >> 424B %vreg4<def> = DIVD %vreg2, %vreg3; G8RC:...

...reg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 > %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 > %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112 > %vreg190<def> = MOVSDrm <fi#0>, 1, %noreg, 120, %noreg; mem:LD8[%85] FR64:%vreg190 > %vreg191<def> = MOVSDrm <fi#0>, 1, %noreg, 96, %noreg; mem:LD8[%87] FR64:%vreg191 > %vreg192<def> = MOVSDrm <fi#0>, 1, %noreg, 88, %noreg; mem:LD8[%92] FR64:%vreg192 > %vreg1...

...GPR64:%vreg1 %vreg0<def> = COPY %X0; GPR64:%vreg0 %vreg16<def> = LS64_LDR <fi#-1>, 0; mem:LD8[FixedStack-1](align=16) GPR64:%vreg16 %vreg17<def> = MOVZxii 42, 0; GPR64:%vreg17 LS64_STR %vreg17<kill>, <fi#-2>, 0; mem:ST8[FixedStack-2](align=16) GPR64:%vreg17 %vreg19<def> = IMPLICIT_DEF; GPR64:%vreg19 %vreg20<def> = IMPLICIT_DEF; GPR32:%vreg20 %vreg18<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg20<kill>, sub_32; GPR64:%vreg18,%vreg19 GPR32:%vreg20 %X0<def> = COPY %vreg18; GPR64:%vreg18 %X1<def> = COPY %vreg18; G...

...Register:i64 %vreg17, t18 t19: i64 = extract_vector_elt t16, Constant:i64<2> t30: ch = CopyToReg t0, Register:i64 %vreg18, t19 t20: i64 = extract_vector_elt t16, Constant:i64<3> t32: ch = CopyToReg t0, Register:i64 %vreg19, t20 t21: i64 = extract_vector_elt t16, Constant:i64<4> t34: ch = CopyToReg t0, Register:i64 %vreg20, t21 t22: i64 = extract_vector_elt t16, Constant:i64<5> t36: ch = CopyToReg t0, Register:i64 %vreg21, t22...