Displaying 20 results from an estimated 20 matches for "vreg18".
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2012 Jun 07
0
[LLVMdev] Instruction Cleanup Questions
...gt; 0x00000000100057c0 <+208>: mr r3,r3
> >
>
> and the RA should eliminate trivial copies.
On PPC, normal moves are encoded as OR instructions where the two
operands being ORed together are the same. These self moves, as it
turns out, come from things like this:
%vreg18<def> = OR8To4 %vreg16, %vreg16; GPRC:%vreg18 G8RC:%vreg16
This is generated from the pattern:
def : Pat<(i32 (trunc G8RC:$in)),
(OR8To4 G8RC:$in, G8RC:$in)>;
So, as far as RA is concerned, this is a "real" operation (a binary OR
which truncates the result to 32-bi...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg1...
2012 Jun 07
4
[LLVMdev] Instruction Cleanup Questions
Hi Hal,
On 07/06/2012 09:57, Chandler Carruth wrote:
> On Wed, Jun 6, 2012 at 10:37 PM, Hal Finkel <hfinkel at anl.gov
> <mailto:hfinkel at anl.gov>> wrote:
>
> I am working on cleaning up some PPC code generation. Two questions:
>
> 1. Which pass is responsible for cleaning up self-moves:
> 0x00000000100057c0 <+208>: mr r3,r3
>
and
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...d from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> %vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
> %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R6...
2012 Jun 07
1
[LLVMdev] Instruction Cleanup Questions
On Jun 7, 2012, at 1:42 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On PPC, normal moves are encoded as OR instructions where the two
> operands being ORed together are the same. These self moves, as it
> turns out, come from things like this:
>
> %vreg18<def> = OR8To4 %vreg16, %vreg16; GPRC:%vreg18 G8RC:%vreg16
>
> This is generated from the pattern:
>
> def : Pat<(i32 (trunc G8RC:$in)),
> (OR8To4 G8RC:$in, G8RC:$in)>;
>
> So, as far as RA is concerned, this is a "real" operation (a binary OR
&...
2012 Jun 07
1
[LLVMdev] Instruction Cleanup Questions
On Jun 7, 2012, at 1:42 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> On PPC, normal moves are encoded as OR instructions where the two
> operands being ORed together are the same. These self moves, as it
> turns out, come from things like this:
>
> %vreg18<def> = OR8To4 %vreg16, %vreg16; GPRC:%vreg18 G8RC:%vreg16
>
> This is generated from the pattern:
>
> def : Pat<(i32 (trunc G8RC:$in)),
> (OR8To4 G8RC:$in, G8RC:$in)>;
>
> So, as far as RA is concerned, this is a "real" operation (a binary OR
&...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...reg4,%vreg2,%vreg3
432B %vreg9<def> = DIVD %vreg7, %vreg8;
G8RC:%vreg9,%vreg7,%vreg8
440B %vreg12<def> = DIVD %vreg10, %vreg11;
G8RC:%vreg12,%vreg10,%vreg11
448B %vreg15<def> = DIVD %vreg13, %vreg14;
G8RC:%vreg15,%vreg13,%vreg14
456B %vreg18<def> = DIVD %vreg16, %vreg17;
G8RC:%vreg18,%vreg16,%vreg17
464B %vreg21<def> = DIVD %vreg19, %vreg20;
G8RC:%vreg21,%vreg19,%vreg20
472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>;
G8RC_and_G8RC_NOX0:%vreg5
480B %vreg6<def> = LDtocL <ga...
2013 Jun 24
1
[LLVMdev] DebugInfo: Missing non-trivially-copyable parameters in SelectionDAG
...;, 0; mem:LD8[FixedStack-1](align=16) GPR64:%vreg16
%vreg17<def> = MOVZxii 42, 0; GPR64:%vreg17
LS64_STR %vreg17<kill>, <fi#-2>, 0; mem:ST8[FixedStack-2](align=16) GPR64:%vreg17
%vreg19<def> = IMPLICIT_DEF; GPR64:%vreg19
%vreg20<def> = IMPLICIT_DEF; GPR32:%vreg20
%vreg18<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg20<kill>, sub_32; GPR64:%vreg18,%vreg19 GPR32:%vreg20
%X0<def> = COPY %vreg18; GPR64:%vreg18
%X1<def> = COPY %vreg18; GPR64:%vreg18
%X2<def> = COPY %vreg18; GPR64:%vreg18
%X3<def> = COPY %vreg18; GPR64:%vr...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
%vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18
%vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
%vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
%vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2
%vreg22&l...
2012 Jul 04
2
[LLVMdev] Assertion in PHIElimination.cpp
...not the
// copy.
Again, no reason is given why only the first terminator is allowed to
use the register.
The offending code is:
(gdb) p opBlock.dump()
BB#8: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#7 BB#22 BB#19 BB#16 BB#11 BB#27 BB#26 BB#25 BB#24 BB#23
%vreg18<def> = COPY %vreg80<kill>; GEXR16:%vreg18,%vreg80
ADJCALLSTACKDOWN 0, %SP<imp-def>, %EX<imp-def>, %SP<imp-use>
CALLi <ga:@clock_get_ticks>, <regmask>, %SP<imp-use>, %SP<imp-def>, %A<imp-def>, ...
ADJCALLSTACKUP 0, 0...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...d from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18
> %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
> %vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
> %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%...
2013 Feb 08
2
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...ause after
line end the stack pointer is pointing to useful data.
Could anyone working on x86 instruction selection give some pointers to
prevent this?
Thanks,
-Peng
ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>,
%ESP<imp-use> ; line 1
%vreg187<def> = COPY %ESP; GR32:%vreg187
; line 2
MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack]
GR32:%vreg187 FR64:%vreg36 ; line 3
%vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
register: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...%vreg9<def> = DIVD %vreg7, %vreg8; G8RC:%vreg9,%vreg7,%vreg8
>> 440B %vreg12<def> = DIVD %vreg10, %vreg11; G8RC:%vreg12,%vreg10,%vreg11
>> 448B %vreg15<def> = DIVD %vreg13, %vreg14; G8RC:%vreg15,%vreg13,%vreg14
>> 456B %vreg18<def> = DIVD %vreg16, %vreg17; G8RC:%vreg18,%vreg16,%vreg17
>> 464B %vreg21<def> = DIVD %vreg19, %vreg20; G8RC:%vreg21,%vreg19,%vreg20
>> 472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>; G8RC_and_G8RC_NOX0:%vreg5
>> 480B %vreg6<...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...Z<kill>; R600_TReg32:%vreg16
> register: %vreg16 +[32r,240r:0)
> 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %vreg18 +[80r,128r:0)
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
>...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...decessors according to CFG: BB#1
%vreg12<def> = mv16Sym <ga:@a>; rN:%vreg12
%vreg13<def> = mv_nimm6_ar16 0; aNlh_rN:%vreg13
mv_ar16_r16_rmod1 %vreg13<kill>, %vreg12<kill>; aNlh_rN:%vreg13 rN:%vreg12
mv_a32_r16_rmod1 %vreg3, %vreg0; aN32_0_7:%vreg3 aNlh_0_7:%vreg0
%vreg18<def> = COPY %vreg0; rN:%vreg18 aNlh_0_7:%vreg0
brr_uncond <BB#6>;
Successors according to CFG: BB#6(0x80000000 / 0x80000000 = 100.00%)
The problem here is the duplicated instruction
mv_a32_r16_rmod1 %vreg3, %vreg0; aN32_0_7:%vreg3 aNlh_0_7:%vreg0
since %vreg0 has register clas...
2013 Feb 08
0
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...ing to useful data.
>
> Could anyone working on x86 instruction selection give some pointers to prevent this?
>
> Thanks,
> -Peng
>
>
> ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1
> %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2
> MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3
> %vreg188<def> = MOV32rm %...
2016 Jul 30
1
Instruction selection bug for vector store with FixedStack
...Selection DAG with the problem:
Optimized legalized selection DAG: BB#16 'foo:vector.body34'
SelectionDAG has 71 nodes:
t0: ch = EntryToken
t6: v8i64,ch = CopyFromReg t0, Register:v8i64 %vreg19
t142: i64,ch = CopyFromReg t0, Register:i64 %vreg18
t143: i64 = add t142, Constant:i64<8>
t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64
t173: i64,ch = load<LD8[FixedStack6](align=64)> t172, FrameIndex:i64<6>,
undef:i64
......
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...Register:i64 %vreg16, t17
t18: i64 = extract_vector_elt t16, Constant:i64<1>
t28: ch = CopyToReg t0, Register:i64 %vreg17, t18
t19: i64 = extract_vector_elt t16, Constant:i64<2>
t30: ch = CopyToReg t0, Register:i64 %vreg18, t19
t20: i64 = extract_vector_elt t16, Constant:i64<3>
t32: ch = CopyToReg t0, Register:i64 %vreg19, t20
t21: i64 = extract_vector_elt t16, Constant:i64<4>
t34: ch = CopyToReg t0, Register:i64 %vreg20, t21...