Displaying 20 results from an estimated 29 matches for "vreg13".
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2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...ill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors according to CFG: BB#1
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
<BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
%vreg5<def> = LDtoc <ga:@a>, %X2; G8RC:%vreg5
%vreg6<def> = LWZ 0, %vreg5; mem:Volatile LD4[@a](tbaa=!"int")
GPRC:%vreg6 G8RC:%vreg5
%vreg7<def> = ADD4 %vreg6<kill>, %vreg3; GPRC:%vreg7,%vreg...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13<def> = BDNZ8 %vreg13, <BB#1>; CTRRC8:%vreg13
> B <BB#2>
> Successors according to CFG: BB#2 BB#1
Phi-elim...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...14:00 -0700
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
>
> > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> > Predecessors according to CFG: BB#0 BB#1
> > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
> > <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 %vreg13<def> = COPY
> > %vreg12<kill>; CTRRC8:%vreg13,%vreg12 %vreg13<def> = BDNZ8 %vreg13,
> > <BB#1>; CTRRC8:%vreg13 B <BB#2>
> > Successors according to CFG: B...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
Hi,
below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
It worked with llvm 3.1, I don't know if there was a requirement introduced betwee...
2017 Apr 24
3
Debugging UNREACHABLE "Couldn't join subrange" in RegisterCoalescer (out-of-tree backend)
...k-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
Here's the tail-end of the log, with debugging turned on:
$llc bugpoint.reduced.simplified.bc -debug
...
208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34
Considering merging to VecRegs with %vreg34 in %vreg13
RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,6...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...uot;. "rN" and "aNlh_0_7" are disjoint.
Is such a PHI node ok?
If it is, then there is a bug in TailDuplication.
Before TailDuplication we have:
BB#2: derived from LLVM BB %bb2
Predecessors according to CFG: BB#1
%vreg12<def> = mv16Sym <ga:@a>; rN:%vreg12
%vreg13<def> = mv_nimm6_ar16 0; aNlh_rN:%vreg13
mv_ar16_r16_rmod1 %vreg13<kill>, %vreg12<kill>; aNlh_rN:%vreg13 rN:%vreg12
brr_uncond <BB#4>;
Successors according to CFG: BB#4(?%)
BB#4: derived from LLVM BB %bb4
Predecessors according to CFG: BB#2 BB#3
%vreg2<def>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...eg27<kill>; R600_Reg128:%vreg3,%vreg27
%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
%vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3
%vreg...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...00_Reg128:%vreg3,%vreg27
> %vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
> %vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
> %vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
> %vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> %vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> %vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> %vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...ons with the loads to
effectively hide the latency.
It seems the issue is with load clustering. I restrict load clustering
to 4 at a time, but when I look at the debug output, the loads are
always being scheduled based on the fact that that are clustered. e.g.
Pick Top CLUSTER
Scheduling SU(10) %vreg13<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 4; mem:LD4[<unknown>] SGPR_32:%vreg13 SReg_128:%vreg9
I have a feeling there is something wrong with my machine model in the
R600 backend, but I've experimented with a few variations of it and have
been unable to solve this problem. Does anyo...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
208B %vreg10<def> = LD 16, %vreg0;
mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
224B %vreg11<def> = LD 16, %vreg1;
mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1
272B %vreg13<def> = LD 24, %vreg0;
mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0
288B %vreg14<def> = LD 24, %vreg1;
mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1
336B %vreg16<def> = LD 32, %vreg0;
mem:LD8[%arrayidx.4](tbaa...
2012 Jan 19
2
[LLVMdev] Best way to interface with MSVC _ftol2 runtime function for fptoui?
...ght. We definitely don't want to model it as a general call, then. Normal calls clobber lots of registers.
The options are:
1. Use a pseudo-instruction that X86FloatingPoint understands and turns into a call after arranging for the argument to be in ST0.
You should emit:
%ST0 = COPY %vreg13; RFP80:%vreg13
%EAX, %EDX = FTOL2 %ST0<kill>
%vreg16 = COPY %EAX<kill>
%vreg17 = COPY %EDX<kill>
Then teach X86FloatingPoint that FTOL2 pops its argument, like FISTP64m.
2. Use inline asm. Which is pretty gross. You would need to construct a SelectionDAG node identic...
2012 Oct 20
0
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vljn at ovi.com> wrote:
> below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
> The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
>
> I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
> It worked with llvm 3.1, I don't know if there was a requirement in...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Successors according to CFG: BB#1
// LOOP CONDITION
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
496B%vreg7<def> = COPY %vreg49<kill>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...ction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
> ... Some COPYs....
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
> 432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
> Successors according to CFG: BB#1
>
>
> // LOOP CONDITION
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
> 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
> 496B%vreg7<...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...t; It seems the issue is with load clustering. I restrict load clustering
> > to 4 at a time, but when I look at the debug output, the loads are
> > always being scheduled based on the fact that that are clustered. e.g.
> >
> > Pick Top CLUSTER
> > Scheduling SU(10) %vreg13<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 4; mem:LD4[<unknown>] SGPR_32:%vreg13 SReg_128:%vreg9
>
> Well, only 4 loads in a sequence should have the “cluster” edges. You should be able to see that when the DAG is printed before scheduling.
>
There are 4 consecutive 'Pick To...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...6
register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
register: %vreg1 replace range with [336r,352r:1) RESULT: [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kill>;...
2012 Jan 20
0
[LLVMdev] Best way to interface with MSVC _ftol2 runtime function for fptoui?
...want to model it as a general call, then. Normal calls clobber lots of registers.
>
> The options are:
>
> 1. Use a pseudo-instruction that X86FloatingPoint understands and turns into a call after arranging for the argument to be in ST0.
> You should emit:
>
> %ST0 = COPY %vreg13; RFP80:%vreg13
> %EAX, %EDX = FTOL2 %ST0<kill>
> %vreg16 = COPY %EAX<kill>
> %vreg17 = COPY %EDX<kill>
>
> Then teach X86FloatingPoint that FTOL2 pops its argument, like FISTP64m.
>
> 2. Use inline asm. Which is pretty gross. You would need to construc...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...48B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
> 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
> R600_TReg32:%vreg17
> register: %vreg1 replace range with [336r,352r:1) RESULT:
> [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> register: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<def> =...
2012 Jan 19
0
[LLVMdev] Best way to interface with MSVC _ftol2 runtime function for fptoui?
2012/1/19 Jakob Stoklund Olesen <stoklund at 2pi.dk>:
> How many of these libcalls do you need to implement? What exactly is the calling convention? Which registers are clobbered etc.
There is only one (that I know about so far). The MSVCRT `_ftol2`
function implements floating-point-to-unsigned conversion for i386
targets, and LLVM 3.0 calls it with the cdecl calling convention for