search for: vreg11

...0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5 %vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10 %vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6 RESERVE_REG 1 RESERVE_REG 2 %vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%vreg11,%vreg9 R600_Reg32:%vreg8 %vreg13<def> = IMPLICIT_DEF; R600_Reg32:%vreg13 %vreg12<def,tied1> = INSERT_SUBREG %vreg11<tied0>, %vreg13, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%...

...reg // R4 = R2 + 4 %R2D<def> = LGR %R4D<kill> // R2 = R4 could be optimized to -> %R2D<def> = LA %R2D<kill>, 4, %noreg // R2 = R2 + 4 The reason this wasn't coalesced, is because of overlapping during coalescing: 864B %vreg11<def> = LA %vreg2, 4, %noreg 880B %vreg16<def> = LLCMux %vreg2, 4, %noreg 928B %vreg2<def> = COPY %vreg11 It seems that if this had been rescheduled to 880B %vreg16<def> = LLCMux %vreg2, 4, %noreg 864B %vreg11<def> = LA %vr...

Hi, Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: %vreg9<def> = IMPLICIT_DEF %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10<def> = IMPLICIT_DEF %vreg10:hi<def> = COPY %vreg1<kill> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10:hi<def,read-undef> = COPY %vreg1<kill>, %vreg10<imp-def&...

...gt; = COPY %X3<kill>; G8RC:%vreg2 %vreg4<def> = LI 2048; GPRC:%vreg4 %vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2 %vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4 %vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9 %vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10 Successors according to CFG: BB#1 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN Predecessors according to CFG: BB#0 BB#1 %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>...

...ng to understand how virtual regs are assigned to operands in IR instructions. I looked into SelectionDAG but could not figure out where the assignment happens. How and where does this conversion happen? Furthermore, I want to build a map between variable and the virtual register (x corresponds to vreg11 in below code). I've been stuck here for a while. Any help is greatly appreciated. C code int main () { int x, y, z; x = 5; y = 6; z = x + y; printf("integer value %d\n", z); return 0; } Generated IR define i32 @main() #0 { entry: %retval = alloca i32, align 4 %x = alloca i32,...

...> of that, I can't seem to get RA to split the following: > > 1 BB#0: derived from LLVM BB %entry > 2 Live Ins: %X3 > 3 %vreg15<def> = COPY %X3; G8RC:%vreg15 > 4 %vreg4<def> = CMPLDI %vreg15, 0; CRRC:%vreg4 G8RC:%vreg15 > 5 %vreg11:sub_32<def,read-undef> = LI 0; G8RC:%vreg11 > 6 BCC 68, %vreg4, <BB#1>; CRRC:%vreg4 > 7 Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) > BB#1(0x50000000 / 0x80000000 = 62.50%) > 8 > 9 BB#4: > 10 Predecessors according to CF...

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13, <BB#1>; CTRRC8:%vreg13 > B <BB#2> > Successors according to CFG: BB#2 BB#1 Phi-elim works by inserting copi...

...i, > > Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: > > %vreg9<def> = IMPLICIT_DEF > %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi > %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> > => > %vreg10<def> = IMPLICIT_DEF > %vreg10:hi<def> = COPY %vreg1<kill> > %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> > => > %vreg10:hi<def,read-undef> = COPY %vreg1&lt...

...9;ve added). However, despite all of that, I can't seem to get RA to split the following: 1 BB#0: derived from LLVM BB %entry 2 Live Ins: %X3 3 %vreg15<def> = COPY %X3; G8RC:%vreg15 4 %vreg4<def> = CMPLDI %vreg15, 0; CRRC:%vreg4 G8RC:%vreg15 5 %vreg11:sub_32<def,read-undef> = LI 0; G8RC:%vreg11 6 BCC 68, %vreg4, <BB#1>; CRRC:%vreg4 7 Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) BB#1(0x50000000 / 0x80000000 = 62.50%) 8 9 BB#4: 10 Predecessors according to CFG: BB#0 11 B <BB#3...

...sson.com> wrote: Hi, Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: %vreg9<def> = IMPLICIT_DEF %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10<def> = IMPLICIT_DEF %vreg10:hi<def> = COPY %vreg1<kill> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10:hi<def,read-undef> = COPY %vreg1<kill>, %vreg10<im...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...%vreg32; R600_Reg128:%vreg10,%vreg32 %vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 R600_Reg32:%vreg47 %vreg10:sel_w<def> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32 %vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 %vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg49,%vreg38 %vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg32 %vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg10 %vreg49&...

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...:%vreg10,%vreg32 > %vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 R600_Reg32:%vreg47 > %vreg10:sel_w<def> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32 > %vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 > %vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg49,%vreg38 > %vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg32 > %vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg1...

...; [ORD=159] 0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159] 0x1f60d60: i32 = undef [ORD=161] 0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60d60<LD4[%sunkaddr41](tbaa=!"int")> [ORD=161] 0x1f34090: <multiple use> 0x1f5c000: i32 = Register %vreg11 0x1f5f040: <multiple use> 0x1f63760: ch = CopyToReg 0x1f34090, 0x1f5c000, 0x1f5f040 0x1f5f040: <multiple use> 0x1f5ed40: i32 = Constant<1> [ORD=162] 0x1f8d010: i32 = and 0x1f5f040, 0x1f5ed40 [ORD=162] 0x1f5f340: i32 = Constant&...

...#1(20) > > BB#1: > Predecessors according to CFG: BB#0 > %vreg9<def> = COPY %vreg1; GR64:%vreg9,%vreg1 > %vreg10<def> = COPY %vreg7; GR64:%vreg10,%vreg7 > %vreg0<def> = LEA64r %vreg7, 1, %noreg, 8, %noreg; GR64:%vreg0,%vreg7 > %vreg11<def> = COPY %vreg0; GR64:%vreg11,%vreg0 > Successors according to CFG: BB#2 > > BB#2: derived from LLVM BB %while.body > Predecessors according to CFG: BB#2 BB#1 > %vreg4<def> = COPY %vreg11; GR64:%vreg4,%vreg11 > %vreg3<def> = COPY %vreg10;...

...register allocator and coalescer are resisting coalescing the COPY MI's for various reasons - for example, the read-only register class contains too few registers and the live range threshold cancels the coalescing. A simple example (post-ISEL): %vreg2<def> = COPY %C1; GPReg:%vreg2 ... %vreg11<def> = MUL %vreg7, %vreg2; GPreg:%vreg11,%vreg7,%vreg2 I'd want it to propagate %C1 into the MUL, replacing %vreg2. How is this supposed to work? Is there a DAG operation or MF pass that should handle this before regalloc, or some other means? Thanks, Joe -------------- next part ------...

...f1e8>)> t0, t8, undef:i64 t8: i64 = add t7, Constant:i64<4> t7: i64 = add t2, t63 t2: i64,ch = CopyFromReg t0, Register:i64 %vreg97 t1: i64 = Register %vreg97 t63: i64 = shl t4, Constant:i8<2> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg11 t3: i64 = Register %vreg11 t1889: i8 = Constant<2> t5: i64 = Constant<4> t10: i64 = undef t16: v32i32,ch = CopyFromReg t0, Register:v32i32 %vreg14 t15: v32i32 = Register %vreg14 In function: int_to_uchar -------------- next part -------------- An HT...

...) G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0 160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1 208B %vreg10<def> = LD 16, %vreg0; mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tba...