Displaying 20 results from an estimated 40 matches for "vreg10".
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2012 May 09
2
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
Hi,
Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
%vreg9<def> = IMPLICIT_DEF
%vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10<def> = IMPLICIT_DEF
%vreg10:hi<def> = COPY %vreg1<kill>
%vreg12<def> = sub %v...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...ction Live Outs: %R0
0B BB#0: derived from LLVM BB %entry
16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP...
2012 May 09
0
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote:
> Hi,
>
> Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
>
> %vreg9<def> = IMPLICIT_DEF
> %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
> =>
> %vreg10<def> = IMPLICIT_DEF
> %vreg10:hi<def> = COPY %vreg1<kill>
> %v...
2012 May 14
1
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
...LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote:
Hi,
Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
%vreg9<def> = IMPLICIT_DEF
%vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10<def> = IMPLICIT_DEF
%vreg10:hi<def> = COPY %vreg1<kill>
%vreg12<def> = s...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...#0: derived from LLVM BB %entry
> 16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> 48B BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...to the scheduler, it became this:
BB#0: derived from LLVM BB %entry
%vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 <<<<<<<<<<<<<
First use uninitialized vreg10
%vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
%vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
%vreg6&l...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
Andy,
Thanks for reply. I was able to trace the problem to the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
# preds...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...omething
here.
What is this statement
if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
should guarantee? From it there must be more than one definition in MRI.def
for that reg for it to work...
To connect it to the original example... When parsing (BU order) this
instruction:
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
The %vreg10<def> never inserted to VRegDefs, so with next instruction:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
Anti dep on %vreg10 is never created.
Thanks.
Sergei
--
Qualcomm Innovation...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...s:
>
> BB#0: derived from LLVM BB %entry
> %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 <<<<<<<<<<<<< First use uninitialized vreg10
> %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg10,%vreg9
> %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
>...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...COPY %vreg4<kill>; IntRegs:%vreg9,%vreg4
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg0<def> = COPY %vreg9<kill>; IntRegs:%vreg0,%vreg9
> %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 <<<<<<<<<<<<<<<<<<<<<<<<<<< Not defined on first iteration….
> %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0
> %vreg3<d...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that.
I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged.
vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vreg32 lives in the 4 machine blocks
After joining, there are still vreg32 occurence in the machinefunction dump.
Before, the MF dump is :
_________________
# Machine code for function main: Post SSA
Func...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...Ivan
On 25/10/2012 23:01, Vincent Lejeune wrote:
> Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that.
> I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged.
> vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vreg32 lives in the 4 machine blocks
> After joining, there are still vreg32 occurence in the machinefunction dump.
>
> Before, the MF dump is :
> _________________
> # Machine code for...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...MRI.def_begin(Reg)) == MRI.def_end())
>
> should guarantee? From it there must be more than one definition in MRI.def
> for that reg for it to work...
>
>
>
>
> To connect it to the original example... When parsing (BU order) this
> instruction:
>
> SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
>
> The %vreg10<def> never inserted to VRegDefs, so with next instruction:
>
> SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
>
> Anti dep on %vreg10 is never created.
Thanks f...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...t; = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5
register: %vreg36 replace range with [976r,992r:1) RESULT: [976r,992r:1)[992r,1024r:0) 0 at 992r 1 at 976r
1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6
register: %vreg37 +[1008r,1040r:0)
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
register: %vreg10 +[1024r,1120r:0)
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37
register: %vreg10 replace range with [1024r,1040r:1) RESULT: [1024r,1040r:1)[1040r,1120r:0) 0 at 10...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...128:%vreg36
> R600_Reg32:%vreg5
> register: %vreg36 replace range with [976r,992r:1) RESULT:
> [976r,992r:1)[992r,1024r:0) 0 at 992r 1 at 976r
> 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37
> R600_Reg128:%vreg6
> register: %vreg37 +[1008r,1040r:0)
> 1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
> register: %vreg10 +[1024r,1120r:0)
> 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10
> R600_Reg32:%vreg37
> register: %vreg10 replace range with [1024r,1040r:1) RESULT:
> [1024r,1040r...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...%vreg9<def> = COPY %vreg4<kill>; IntRegs:%vreg9,%vreg4
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg0<def> = COPY %vreg9<kill>; IntRegs:%vreg0,%vreg9
%vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
<<<<<<<<<<<<<<<<<<<<<<<<<<< Not defined on first iteration..
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
%vreg3<def>...
2014 Oct 27
4
[LLVMdev] Problem in X86 backend
Hi,
I'm having some trouble wirting an instruction in the X86 backend.
I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend.
Everything works fine, except for one instruction that I can't find how to write.
I want to add this instruction in one of my machine basic block: mov [rdi], 0
How can I achieve that with the LLVM api? I tried several
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
On Mon, 11 Jun 2012 10:48:18 -0700
Andrew Trick <atrick at apple.com> wrote:
> On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> > I'm considering writing more-detailed itineraries for some PowerPC
> > CPUs that use the 'traditional' instruction grouping scheme. In
> > essence, this means that multiple instructions will stall