Displaying 6 results from an estimated 6 matches for "vramsz".
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vram
2014 Feb 10
0
[PATCH] drm/nouveau: support for platform devices
...e080899a 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
> @@ -349,7 +349,7 @@ nv20_graph_init(struct nouveau_object *object)
> nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
>
> /* begin RAM config */
> - vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
> + vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
In case BAR0 is of size zero (start == 0, end == start), this will cause
underflow in the case of a PCI device, because pci_resource_len() will
return 0. I suspect that this never h...
2014 Feb 10
2
[PATCH] drm/nouveau: support for platform devices
...aph/nv20.c
index b24559315903..d145e080899a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
@@ -349,7 +349,7 @@ nv20_graph_init(struct nouveau_object *object)
nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
/* begin RAM config */
- vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
+ vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
diff --git a/drivers/gpu/drm/no...
2014 Feb 11
2
[PATCH] drm/nouveau: support for platform devices
.../gpu/drm/nouveau/core/engine/graph/nv20.c
>> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
>> @@ -349,7 +349,7 @@ nv20_graph_init(struct nouveau_object *object)
>> nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
>>
>> /* begin RAM config */
>> - vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
>> + vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
>
> In case BAR0 is of size zero (start == 0, end == start), this will cause
> underflow in the case of a PCI device, because pci_resource_len() will
> return 0....
2014 Feb 12
0
[PATCH v2] drm/nouveau: support for platform devices
...aph/nv20.c
index b24559315903..d145e080899a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
@@ -349,7 +349,7 @@ nv20_graph_init(struct nouveau_object *object)
nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
/* begin RAM config */
- vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
+ vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
diff --git a/drivers/gpu/drm/no...
2009 Dec 11
5
[PATCH 1/3] drm/nouveau: Pre-G80 tiling support.
..., addr, size, pitch);
+
+ pgraph->fifo_access(dev, true);
+ pfifo->reassign(dev, true);
+}
+
/*
* G70 0x47
* G71 0x49
@@ -347,7 +408,8 @@ nv40_graph_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv =
(struct drm_nouveau_private *)dev->dev_private;
- uint32_t vramsz, tmp;
+ struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
+ uint32_t vramsz;
int i, j;
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -425,74 +487,9 @@ nv40_graph_init(struct drm_device *dev)
nv_wr32(dev, 0x400b38, 0x2ffff800);
nv_wr32(dev, 0x400b3c, 0x000...
2014 Feb 12
2
[PATCH v2] drm/nouveau: support for platform devices
On 12/02/14 05:38, Alexandre Courbot wrote:
> Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead
> of PCI to which Nouveau is tightly dependent. This patch allows Nouveau
> to handle platform devices by:
>
> - abstracting PCI-dependent functions that were typically used for
> resource querying and page mapping,
> - introducing a nv_device_is_pci()