search for: vr_mutex

...gt; + } > + > + return 0; > +} > + > +#define PROCESS_DESC_CHAIN true > + > +/* Copy a specified number of virtio descriptors in a chain */ > +int mic_virtio_copy_desc(struct mic_vdev *mvdev, > + struct mic_copy_desc *request) > +{ > + int err; > + struct mutex *vr_mutex; > + > + err = verify_copy_args(mvdev, &request->copy); > + if (err) > + return err; > + > + vr_mutex = &mvdev->vr_mutex[request->copy.vr_idx]; > + mutex_lock(vr_mutex); > + if (!mic_vdevup(mvdev)) { > + err = -ENODEV; > + dev_err(mic_dev(mvdev), &q...

...d\n", + __func__, __LINE__, -EINVAL); + return -EINVAL; + } + + return 0; +} + +#define PROCESS_DESC_CHAIN true + +/* Copy a specified number of virtio descriptors in a chain */ +int mic_virtio_copy_desc(struct mic_vdev *mvdev, + struct mic_copy_desc *request) +{ + int err; + struct mutex *vr_mutex; + + err = verify_copy_args(mvdev, &request->copy); + if (err) + return err; + + vr_mutex = &mvdev->vr_mutex[request->copy.vr_idx]; + mutex_lock(vr_mutex); + if (!mic_vdevup(mvdev)) { + err = -ENODEV; + dev_err(mic_dev(mvdev), "%s %d err %d\n", + __func__, __LINE__,...

...d\n", + __func__, __LINE__, -EINVAL); + return -EINVAL; + } + + return 0; +} + +#define PROCESS_DESC_CHAIN true + +/* Copy a specified number of virtio descriptors in a chain */ +int mic_virtio_copy_desc(struct mic_vdev *mvdev, + struct mic_copy_desc *request) +{ + int err; + struct mutex *vr_mutex; + + err = verify_copy_args(mvdev, &request->copy); + if (err) + return err; + + vr_mutex = &mvdev->vr_mutex[request->copy.vr_idx]; + mutex_lock(vr_mutex); + if (!mic_vdevup(mvdev)) { + err = -ENODEV; + dev_err(mic_dev(mvdev), "%s %d err %d\n", + __func__, __LINE__,...

An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after

An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v1 => v2: a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lkml.org/lkml/2013/7/24/810 Description:

ChangeLog: ========= v1 => v2: a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lkml.org/lkml/2013/7/24/810 Description: