Displaying 4 results from an estimated 4 matches for "vr2048".
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vr_2048
2017 Jul 07
2
Unhandled reg/opcode register encoding VR2048 Error in backend
Hello,
I m working towards backend.
Here i need to define vector load and stores for 64 i32 elements. so in
x86instrinfo.td i wrote;
def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
"vmov_256B_rm\t{$src, $dst|$dst, $src}",
[(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],
IIC_MOV_MEM>, EVEX;
def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst,...
2017 Jul 08
5
Error in v64i32 type in x86 backend
...t;> Keep I
>>>
>>> ~Craig
>>>
>>> On Fri, Jul 7, 2017 at 10:28 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>> wrote:
>>>
>>>> I keep this one;
>>>>
>>>> def VADD_256B : I<0xFE, MRMDestReg, (outs VR2048:$dst), (ins VR2048:$src1,
>>>> VR2048:$src2),
>>>> "VADD_256B\t{$dst, $src1, $src2 }", [(set VR2048:$dst,
>>>> (add VR2048:$src1, VR2048:$src2))]>;
>>>>
>>>> On Sat, Jul 8, 2017 at 10:17 AM, hameeza ahmed &l...
2017 Jul 08
2
Error in v64i32 type in x86 backend
Thank you;
i have changed as follows.is it fine now?
def VADD_256B : I<0xFE, MRMDestReg, (outs VR2048:$dst), (ins VR2048:$src1,
VR2048:$src2),
"VADD_256B\t{$src, $dst|$dst, $src}", [(set VR2048:$dst,
(add VR2048:$src1, VR2048:$src2))]]>;
Also here i have changed class RI to I. Does it make any difference?
On Sat, Jul 8, 2017 at 9:38 AM, Craig Topper <craig.top...
2017 Jul 08
2
Error in v64i32 type in x86 backend
Thank you. i understood how avx512 vector instructions are written in
x86instravx512. i need to define my vector instructions so i wrote;
def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
"vmov_256B_rm\t{$src, $dst|$dst, $src}",
[(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],
IIC_MOV_MEM>, EVEX;
def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst,...