Displaying 20 results from an estimated 30 matches for "vpu".
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2007 Apr 05
4
[LLVMdev] Integrating LLVM in an existing project
...h university Pierre et Marie Curie in
Paris. I work on a project
called the "Virtual Virtual Machine" project. You can find some (dated)
information on the
website http://vvm.lip6.fr.
Basically it's a "low level virtual machine" :) with a just in time
compiler called the VPU, an execution environment
(GC + threads) and it parses a lisp-like language that is translated to
the VPU's internal bytecode.
On top of this execution environment we have implemented a java virtual
machine and a .net virtual machine. They
are both functional and we achieve reasonable perfor...
2008 May 29
4
pass multicore cpu to domU?
...tly.
I have a server that has 2xquad core xeons. Among other things, there
is a windows based statistical app that we need to be able to run.
This app is smp enabled, and I would like to allocate either one or
both physical cpus to it.
As I understand it, is that xen treats each core as a vpu, and the
concept of a ''quad-core cpu'' is lost.
The problem I am facing is that, because the app is windows based, I
obviously need to use a windows guest. Windows XP will only recognise
up to 2 cpus. According to other sources I''ve read, it bases this
restricti...
2007 Apr 05
0
[LLVMdev] Integrating LLVM in an existing project
...in
> Paris. I work on a project
> called the "Virtual Virtual Machine" project. You can find some (dated)
> information on the
> website http://vvm.lip6.fr.
>
> Basically it's a "low level virtual machine" :) with a just in time
> compiler called the VPU, an execution environment
> (GC + threads) and it parses a lisp-like language that is translated to
> the VPU's internal bytecode.
Interesting project. I wish you could talk about it at the Developer's
Meeting (http://llvm.org/DevMtgMay2007.html :)
.. snip ..
> So here are a fe...
2017 Feb 22
3
[Proposal][RFC] Epilog loop vectorization
Hi,
This is a proposal about epilog loop vectorization.
Currently Loop Vectorizer inserts an epilogue loop for handling loops that don't have known iteration counts.
The Loop Vectorizer supports loops with an unknown trip count, unknown trip count may not be a multiple of the vector width, and the vectorizer has to execute the last few iterations as scalar code. It keeps a scalar copy of
2017 Feb 23
2
[Proposal][RFC] Epilog loop vectorization
...uting scalar iterations.
>> This require following changes:
>> 1)Costing: Preserve all profitable vector factor.
>> 2)Transform: Create an additional vector loop with next profitable
>> vector factor.
>
> Is this something that you propose to be on by default for wide VPU
> architectures without masking support? I.e. how widely is this
> applicable? If not then perhaps a better strategy would be to just
> annotate the remainder loop with some metadata to limit the
> vectorization factor and just rerun the vectorizer.
Why would this solution (annot...
2008 Mar 28
0
[LLVMdev] Say hi to VMKit: JVM/LLVM, CLI/LLVM
On Friday 21 March 2008 21:52:32 Nicolas Geoffray wrote:
> Hi everyone,
>
> I've just checked in a JVM and a CLI for LLVM (called JnJVM and N3).
> Both are placed in the vmkit svn directory.
> You can find the source code here:
>
> svn co http://llvm.org/svn/llvm-project/vmkit/trunk vmkit
This looks really exciting but I'm having trouble finding information about
2012 Aug 28
2
[LLVMdev] How to write a regression test case?
...RUN: FileCheck < %t.s %s
// CHECK: fct
unsigned int fct(unsigned int n) {
if(n>0) return fct(n-1)*n;
else return 1;
}
/* end example.c */
/* lit.local.cfg */
config.suffixes = ['.c', '.cpp', '.ll']
targets = set(config.root.targets_to_build.split())
if not 'VPU' in targets:
config.unsupported = True
/* end lit.local.cfg */
2012/8/28 Changcheng Wang <changcheng at multicorewareinc.com>:
> hi,yang:
> thanks for your help!
> my net is so poor that i can not donwload your attachment.
> would you like to paste here,or send to my oth...
2012 Aug 28
3
[LLVMdev] How to write a regression test case?
...turn fct(n-1)*n;
>> else return 1;
>> }
>> /* end example.c */
>>
>>
>> /* lit.local.cfg */
>> config.suffixes = ['.c', '.cpp', '.ll']
>>
>> targets = set(config.root.targets_to_build.split())
>> if not 'VPU' in targets:
>> config.unsupported = True
>> /* end lit.local.cfg */
>>
>>
>> 2012/8/28 Changcheng Wang <changcheng at multicorewareinc.com>:
>>> hi,yang:
>>> thanks for your help!
>>> my net is so poor that i can not donwload y...
2007 Dec 20
5
[PATCH 0/16] lguest: introduce vcpu structure
this patch makes room for the vcpu structure in lguest, already used in
this very same way at lguest64. It's the first part of our plan to
have lguest and lguest64 unified too.
When two dogs hang out, you don't have new puppies right in the other day.
Some time has to be elapsed. They have to grow first. In this same spirit, having these
patches _do not_ mean smp guests can be launched
2007 Dec 20
5
[PATCH 0/16] lguest: introduce vcpu structure
this patch makes room for the vcpu structure in lguest, already used in
this very same way at lguest64. It's the first part of our plan to
have lguest and lguest64 unified too.
When two dogs hang out, you don't have new puppies right in the other day.
Some time has to be elapsed. They have to grow first. In this same spirit, having these
patches _do not_ mean smp guests can be launched
2014 May 28
2
[LLVMdev] Partially complete LLVM backend for the VideoCore 4
Hello,
For a while I've been working on an LLVM backend for Broadcom's
VideoCore 4, the GPU made famous by the Raspberry Pi. This isn't the
QPU, for which Broadcom released docs a little while ago; it's the main
processor, which is a VC4 core.
It's a rather elegant thing with two cores, 32 registers, a built-in DSP
and an extremely nice instruction set; reverse engineered
2012 Aug 28
3
[LLVMdev] How to write a regression test case?
Wang,
Attachment is a simple example, you may put it in test/CodeGen, and run with
llvm-lit C90
It worked ok in my llvm 3.2 devel. Let know if you run into any trouble.
Regards.
2012/8/27 Changcheng Wang <changcheng at multicorewareinc.com>:
> hi,Yang:
> if you can give me a examle,which check out a string(such as "abcd")
> from a file(such as aaa.c) with fileCheck?
2012 Aug 28
0
[LLVMdev] How to write a regression test case?
...se return 1;
>>> }
>>> /* end example.c */
>>>
>>>
>>> /* lit.local.cfg */
>>> config.suffixes = ['.c', '.cpp', '.ll']
>>>
>>> targets = set(config.root.targets_to_build.split())
>>> if not 'VPU' in targets:
>>> config.unsupported = True
>>> /* end lit.local.cfg */
>>>
>>>
>>> 2012/8/28 Changcheng Wang <changcheng at multicorewareinc.com>:
>>>> hi,yang:
>>>> thanks for your help!
>>>> my net is s...
2017 Feb 27
4
[Proposal][RFC] Epilog loop vectorization
...or and has a high possibility of executing scalar iterations.
This require following changes:
1) Costing: Preserve all profitable vector factor.
2) Transform: Create an additional vector loop with next profitable vector factor.
Is this something that you propose to be on by default for wide VPU architectures without masking support? I.e. how widely is this applicable? If not then perhaps a better strategy would be to just annotate the remainder loop with some metadata to limit the vectorization factor and just rerun the vectorizer.
Why would this solution (annotating the remainder loop...
2012 Aug 28
0
[LLVMdev] How to write a regression test case?
...gned int n) {
> if(n>0) return fct(n-1)*n;
> else return 1;
> }
> /* end example.c */
>
>
> /* lit.local.cfg */
> config.suffixes = ['.c', '.cpp', '.ll']
>
> targets = set(config.root.targets_to_build.split())
> if not 'VPU' in targets:
> config.unsupported = True
> /* end lit.local.cfg */
>
>
> 2012/8/28 Changcheng Wang <changcheng at multicorewareinc.com>:
>> hi,yang:
>> thanks for your help!
>> my net is so poor that i can not donwload your attachment.
>> would y...
2017 Jun 21
2
AVX 512 Assembly Code Generation issues
when i generate code with 72 loop iterations.
the compiler generates code with using avx512 zmm operations 4 times
(16x4=64) and remaining 8 iterations are handled by routine mov operations
with EAX register. wouldn't it be better if it uses ymm for remaining 8
iterations as it does when iteration count is between 8 and 15. same for
xmm and so on.
please correct me if i am wrong.
Thank
2019 Sep 30
3
Adding support for vscale
On Tuesday, October 1, 2019, Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Mon, Sep 30, 2019 at 2:30 AM Sander De Smalen via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> >
> > I've posted two patches on Phabricator to add support for VScale in LLVM.
Excellent!
> >
> > A brief recap on `vscale`:
> > The scalable vector type in
2012 Aug 28
4
[LLVMdev] How to write a regression test case?
...>>> /* end example.c */
>>>>
>>>>
>>>> /* lit.local.cfg */
>>>> config.suffixes = ['.c', '.cpp', '.ll']
>>>>
>>>> targets = set(config.root.targets_to_build.split())
>>>> if not 'VPU' in targets:
>>>> config.unsupported = True
>>>> /* end lit.local.cfg */
>>>>
>>>>
>>>> 2012/8/28 Changcheng Wang <changcheng at multicorewareinc.com>:
>>>>> hi,yang:
>>>>> thanks for your help!...
2018 Aug 06
2
vectorisation, risc-v
(please do cc me to preserve thread as i am subscribed digest)
Hi folks, i have a requirement to develop a libre licensed low power
embedded 3D GPU and VPU and using RISCV as the basis (GPGPU style) seems
eminently sensible, and anyone is invited to participate. A gsoc2017
student named Jake has already developed a Vulkan3D software renderer and
shader, and (parallelised) llvm is a critical dependency to achieving the
high efficiency needed. The diff...
2019 Oct 01
3
Adding support for vscale
...as an intrinsic which always returns the same
> value during one program execution.
>
> Luckily, this is not a problem for RVV. I do not know anything about this
> "SV" extension you are working on
SV has been designed specifically to help with the creation of
*Hybrid* CPU / VPU / GPUs. it's very similar to RVV except that there
are no new instructions added.
a typical GPU would be happy to have 128-bit-wide SIMD or VLIW-style
instructions, on the basis that (A) the shader programs are usually no
greater than 1K in size and (B) those 128-bit-wide instructions have
an...