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2020 Jun 25
2
How to implement load/store for vector predicate register
...compare flag.
We have defined registers and a new type(vpr) for vector predicate registers in backend.
Although there is no direct instruction to move vpr to vr or to move vr to vpr, there is a method to work around this. And we have load/store instructions for vr.
move vpr to vr for v32i16 (from vpr0 to vr1):
1 vclr vr0 // clear vr0
2 ldi r5, 0x00010001 // load immediate (compare bit mask for v32i16) to scalar register r5
3 movr2vr.dup vr2, r5 // duplicate content in r5 into vr2,
4 vadd.t.s16 vr1, vr0, vr2, vpr0 //vector add if element compare bit is set, element t...
2020 Jun 26
2
How to implement load/store for vector predicate register
...compare flag.
We have defined registers and a new type(vpr) for vector predicate registers in backend.
Although there is no direct instruction to move vpr to vr or to move vr to vpr, there is a method to work around this. And we have load/store instructions for vr.
move vpr to vr for v32i16 (from vpr0 to vr1):
1 vclr vr0 // clear vr0
2 ldi r5, 0x00010001 // load immediate (compare bit mask for v32i16) to scalar register r5
3 movr2vr.dup vr2, r5 // duplicate content in r5 into vr2,
4 vadd.t.s16 vr1, vr0, vr2, vpr0 //vector add if element compare bit is set, element t...