search for: vppr

...ing, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update RVI/SVI to make APIC-v working accordingly. Changes from V2: * Rebase on top of Xen upstream * Merge patch 1(Introduce interrupt source supporting) and patch 3(Add interface to update vPPR) into the place where there were used. * Reorder the patch set. Yang Zhang (4): Nested VMX: Check whether interrupt is blocked by TPR Nested VMX: Force check ISR when L2 is running Nested VMX: Clear APIC-v control bit in vmcs02 Nested VMX: Update APIC-v(RVI/SVI) when vmexit to L1 x...