Displaying 6 results from an estimated 6 matches for "vpmu_core2".
2012 Feb 29
0
[PATCH] vpmu: cleanup structures
...p of vpmu structures:
- struct msr_load_store_entry is unused
- struct pmumsr is only used in the vmx part
Dietmar.
Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
# HG changeset patch
# Parent a7bacdc5449a2f7bb9c35b2a1334b463fe9f29a9
diff -r a7bacdc5449a xen/arch/x86/hvm/vmx/vpmu_core2.c
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c Mon Feb 27 17:05:18 2012 +0000
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c Wed Feb 29 10:42:56 2012 +0100
@@ -112,6 +112,11 @@ u32 core2_ctrls_msr[] = {
MSR_IA32_PEBS_ENABLE,
MSR_IA32_DS_AREA};
+struct pmumsr {
+ unsigned int num;
+ u32 *msr;...
2013 Mar 12
0
[PATCH] vpmu intel: pass through cpuid bits when BTS is enabled
...RE_DTES64
(64-bit DS Area) and X86_FEATURE_DSCPL (CPL Qualified Debug Store) to the
guest when the BTS feature is switched on.
I forgot this when I did this BTS emulation.
Thanks.
Dietmar.
Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
diff -r a6b81234b189 xen/arch/x86/hvm/vmx/vpmu_core2.c
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c Mon Mar 11 16:13:42 2013 +0000
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c Tue Mar 12 13:58:40 2013 +0100
@@ -607,6 +607,10 @@ static void core2_vpmu_do_cpuid(unsigned
{
/* Switch on the ''Debug Store'' feature in CPUID.EAX...
2013 Apr 09
39
[PATCH 0/4] Add posted interrupt supporting
...| 4 +-
xen/arch/x86/hvm/vlapic.c | 19 +++++-
xen/arch/x86/hvm/vmsi.c | 5 +-
xen/arch/x86/hvm/vmx/vmcs.c | 18 +++++-
xen/arch/x86/hvm/vmx/vmx.c | 81 ++++++++++++++++++++++++
xen/arch/x86/hvm/vmx/vpmu_core2.c | 5 +-
xen/arch/x86/hvm/vpt.c | 10 ++-
xen/include/asm-x86/hvm/hvm.h | 2 +
xen/include/asm-x86/hvm/vlapic.h | 1 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 13 ++++
xen/include/asm-x86/hvm/vmx/vmx.h...
2012 May 30
12
[PATCH v2 0/4] XEN: fix vmx exception mistake
Changes from v1:
- Define new struct hvm_trap to represent information of trap, include
instruction length.
- Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of
wrappers around that function for existing callers, so that their parameter
lists actually *shrink*.
This series of patches fix the mistake for debug exception(#DB), overflow
exception(#OF) and INT3(#BP),
2007 Dec 11
13
[PATCH] Enable Core 2 Duo Performance Counters in HVM guest
Hi, Keir,
Currently, HVM guests do not have access to performance counters. So it
is not possible to use performance analyzer software such as vtune in
HVM guest to analyze programme performance. Other usage of performance
counters , for example, the NMI watchdog, won''t function either.
This patch will enable performance counters in HVM guest. Currently,
only Core 2 Duo is implemented.
2013 Mar 12
14
vpmu=1 and running 'perf top' within a PVHVM guest eventually hangs dom0 and hypervisor has stuck vCPUS. Romley-EP (model=45, stepping=2)
This issue I am encountering seems to only happen on multi-socket
machines.
It also does not help that the only multi-socket box I have is
an Romley-EP (so two socket SandyBridge CPUs). The other
SandyBridge boxes I''ve (one socket) are not showing this. Granted
they are also a different model (42).
The problem is that when I run ''perf top'' within an SMP PVHVM
guest,