Displaying 2 results from an estimated 2 matches for "vpll_s2".
2016 Mar 02
0
Debugging second dvi output on quadro fx380 not working
...0x3 | UNK12 = 0 | UNK23 = 0 | UNK28 }
[0] 108.303439 MMIO32 R 0x614104 0x00020016 PDISPLAY.CLOCK.VPLL_S1[0] => { N1 = 0x16 | M1 = 0x2 }
[0] 108.303452 MMIO32 W 0x614104 0x00020016 PDISPLAY.CLOCK.VPLL_S1[0] <= { N1 = 0x16 | M1 = 0x2 }
[0] 108.303466 MMIO32 R 0x614108 0x2007000e PDISPLAY.CLOCK.VPLL_S2[0] => { N2 = 0xe | M2 = 0x7 | P = 0x2 }
[0] 108.303479 MMIO32 W 0x614108 0x2007000e PDISPLAY.CLOCK.VPLL_S2[0] <= { N2 = 0xe | M2 = 0x7 | P = 0x2 }
[0] 108.303493 MMIO32 R 0x610ad0 0x00824414 PDISPLAY.CRTC_VAL[0].CLOCK[0] => 0x824414
[0] 108.303507 MMIO32 R 0x610b58 0x00000000 PDISPLAY.DAC_...
2016 Oct 12
0
[PATCH] rnndb: add some definitions from nvreg.h for pramdac
...1:NV20 NV25:NV30 NV31:G80" type="nv3_pll"/>
<reg32 offset="0x520" name="VPLL2" variants="NV30:NV31" type="nv30_pll"/>
+ <reg32 offset="0x524" name="SEL_CLK"/>
<reg32 offset="0x570" name="NVPLL_S2" variants="NV31:NV34" type="nv31_pll_s2"/>
<reg32 offset="0x574" name="MPLL_S2" variants="NV31:NV34" type="nv31_pll_s2"/>
<reg32 offset="0x578" name="VPLL_S2" variants="NV31:NV34" type=&qu...