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...ster region parameters in the bitcast instruction( from qword with hstride 1 to dword with hstride 2) At which stage is suitable to do such bitcast instruction logic? after reg-alloc? The detailed hardware spec is located at: https://01.org/sites/default/files/documentation/intel-gfx- prm-osrc-bdw-vol07-3d_media_gpgpu_3.pdf at page 921, it describe the detailed instruction encode format. It needs (regFile, regNum, subRegNum, width, type, addrMode, hStride, vStride) to describe a register. I have attached my first version RegisterInfo.td. And I also have a question about the attached RegisterInfo....

...public = true # hide dot files = yes # preserve case = yes # short preserve case = yes #[scanner2] # path = /vol06/scanner # create mask = 4777 # writeable = true # public = true # hide dot files = yes # default case = lower # preserve case = yes # short preserve case = yes [ctp_01] path = /vol07/platte_07 create mask = 4777 writeable = yes public = true hide dot files = yes default case = lower short preserve case = yes #[platte_08] # path = /vol08/platte_08 # writeable = no # public = true # hide dot files = yes #...