search for: vmull

...in d11 top in all case, + * so we will store reduce the 4 four top result of vector operation */ + ".celt_fir4_process_remaining_%=:\n" + "vld1.16 d0[0], [%0]!;\n" //Load x + "vshll.s16 q7, d0, %[SIGSHIFT];\n" //Initialize sum + "vmull.s16 q8, d4, d11;\n" //Multiply-accumulate + "vadd.s32 d16, d16, d17;\n" //Three next instructions reduce the sum + "vpadd.s32 d16, d16;\n" + "vadd.s16 d14, d14, d16;\n" + "vrshrn.s32 d6, q7, %[SIGSHIFT];\n" //Scale resu...

...in d11 top in all case, + * so we will store reduce the 4 four top result of vector operation */ + ".celt_fir4_process_remaining_%=:\n" + "vld1.16 d0[0], [%0]!;\n" //Load x + "vshll.s16 q7, d0, %[SIGSHIFT];\n" //Initialize sum + "vmull.s16 q8, d4, d11;\n" //Multiply-accumulate + "vadd.s32 d16, d16, d17;\n" //Three next instructions reduce the sum + "vpadd.s32 d16, d16;\n" + "vadd.s16 d14, d14, d16;\n" + "vrshrn.s32 d6, q7, %[SIGSHIFT];\n" //Scale resu...

...uint32_t remainder = len % 16; + len = len - remainder; + + asm volatile (" cmp %[len], #0\n" + " bne 1f\n" + " vld1.16 {d16}, [%[b]]!\n" + " vld1.16 {d20}, [%[a]]!\n" + " subs %[remainder], %[remainder], #4\n" + " vmull.s16 q0, d16, d20\n" + " beq 5f\n" + " b 4f\n" + "1:" + " vld1.16 {d16, d17, d18, d19}, [%[b]]!\n" + " vld1.16 {d20, d21, d22, d23}, [%[a]]!\n" + " subs %[len], %[len], #16\n" + " vmull.s16 q0, d16,...

From: Jyri Sarha <jsarha at ti.com> I optimized Speex resampler for NEON capable ARM CPUs. The first patch should speed up resampling on any platform that can spare the increased memory usage. It would be nice to have these merged to the master branch. Please let me know if there is anything I can do to help the the merge. The patches have been rebased on top of master branch in