Displaying 8 results from an estimated 8 matches for "vmrs".
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2010 Jul 12
0
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
> ~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr
> -melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o
Ok, this way you're generating code for x86
> /usr/lib/crti.o
> /usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o
> -L/usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0 -L/usr/local/lib -lgcc
> --as-needed -lgcc_s --no-as-needed -lc -lgcc
2010 Jul 28
2
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
..../gcc/../include -I../.././gcc/../libcpp/include
-I../.././gcc/../libdecnumber -I../libdecnumber -I/home/jal/llvm-2.7/include
-DL_mulsc3 -fvisibility=hidden -DHIDE_EXPORTS -c ../.././gcc/libgcc2.c -o
libgcc/./_mulsc3.o
/tmp/ccmyj0Hi.s: Assembler messages:
/tmp/ccmyj0Hi.s:60: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:62: Error: bad instruction `vmrsvs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:71: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:76: Error: bad instruction `vmrs apsr_nzcv,fpscr'
/tmp/ccmyj0Hi.s:83: Error: bad instruction `vmrs apsr_nzcv,fpscr...
2010 Jul 12
2
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
Sorry for not explaining well.
After compiling with g++-cross
g++-cross -c a.c
I do link using this command
/gold_binutils/build/gold/ld-new -plugin
~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr
-melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o
/usr/lib/crti.o
/usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o
2013 May 30
9
[PATCH v2 0/2] Implement VFP context switch for arm32
Hello,
This is the second version of this patch series.
I only implement the VPF context switch support for arm32 and add dummy function
to avoid compilation on arm64.
I have switched the order of the patch because the old second one can be applied
alone and the patch are cleaner :).
For all the changes see each patch.
Cheers,
Julien Grall (2):
xen/arm: don''t enable VFP on XEN
2019 Oct 08
2
PR43374 - when should comparing NaN values raise a floating point exception?
...Now, send the optimized IR to codegen:
> define i32 @is_nan(float %x) {
> %cmp = fcmp uno float %x, 0.000000e+00
> %r = zext i1 %cmp to i32
> ret i32 %r
> }
>
> $ llc -o - fpexception.ll -mtriple=armv7a
> vmov s0, r0
> mov r0, #0
> vcmpe.f32 s0, s0
> vmrs APSR_nzcv, fpscr
> movwvs r0, #1
> bx lr
>
> We produced "vcmpe" for code that should never cause an FP exception. ARM
> codegen bug?
sorry, the arm code gen is right here, the bug is in clang.
>
> On Tue, Oct 1, 2019 at 5:45 AM Kristof Beyls <Kristof.Beyls...
2011 May 26
2
[LLVMdev] LLVM CodeGen Engineer job opening with Apple's compiler team
Hi all,
LLVM CodeGen and Tools team at Apple is looking for exceptional compiler engineers. This is a great opportunity to work with many of the leaders in the LLVM community.
If you are interested in this position, please send your resume / CV and relevant information to evan.cheng at apple.com
Thanks,
Evan
Job description
The Apple compiler team is seeking an engineer who is strongly
2011 May 27
1
[LLVMdev] Question about ARM/vfp/NEON code generation
...str r1, [r7, #-8]
vmov s1, r1
str r2, [r7, #-12]
vmov s2, r2
vldr.32 s3, [r7, #-4]
vldr.32 s4, [r7, #-8]
vmul.f32 s3, s3, s4
vstr.32 s3, [r7, #-16]
vldr.32 s4, [r7, #-12]
vcmpe.f32 s3, s4
vmrs apsr_nzcv, fpscr
vstr.32 s0, [sp, #16]
vstr.32 s2, [sp, #12]
vstr.32 s1, [sp, #8]
ble LBB20_2
@ BB#1: @ %bb
vldr.32 s0, [r7, #-16]
ldr r0, LCPI20_0
LPC20_0:
add r0, pc, r0
vcvt.f64.f32...
2019 Oct 01
5
PR43374 - when should comparing NaN values raise a floating point exception?
Hi,
I’ve been investigating https://bugs.llvm.org/show_bug.cgi?id=43374, which is about clang/llvm producing code that triggers a floating point exception when x is NaN, when targeting ARM, in the below code example.
int bar(float x) {
return x!=x ? 0 : 1;
}
The C99 standard states in section 7.12.14:
"""
The relational and equality operators support the usual mathematical