search for: vmovntp

...pher [mailto:echristo at gmail.com] Sent: Sunday, May 01, 2016 19:54 To: Zuckerman, Michael <michael.zuckerman at intel.com>; Craig Topper <craig.topper at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] r267690 - [Clang][BuiltIn][AVX512]Adding intrinsics for vmovntdqa vmovntpd vmovntps instruction set Why? On Sun, May 1, 2016, 6:04 AM Zuckerman, Michael via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hi, For now no. But I will add this three builtins to CGBuiltin.cpp. If you want, you can be a reviewer of this change. Re...

...you can be a reviewer of this change. Regards Michael Zuckerman From: Craig Topper [mailto:craig.topper at gmail.com] Sent: Thursday, April 28, 2016 04:53 To: Zuckerman, Michael <michael.zuckerman at intel.com> Subject: Re: r267690 - [Clang][BuiltIn][AVX512]Adding intrinsics for vmovntdqa vmovntpd vmovntps instruction set Can we use native IR for the stores the way the 128-bit and 256-bit equivalents do? On Wed, Apr 27, 2016 at 3:44 AM, Michael Zuckerman via cfe-commits <cfe-commits at lists.llvm.org<mailto:cfe-commits at lists.llvm.org>> wrote: Author: mzuckerm Date: Wed Apr...

...+ if ( vex_pfx ) \ + (dst) = sse_prefix[(vex_pfx) - 1]; \ +} while (0) + union vex { uint8_t raw[2]; struct { @@ -3850,6 +3860,76 @@ x86_emulate( case 0x19 ... 0x1f: /* nop (amd-defined) */ break; + case 0x2b: /* {,v}movntp{s,d} xmm,m128 */ + /* vmovntp{s,d} ymm,m256 */ + fail_if(ea.type != OP_MEM); + /* fall through */ + case 0x28: /* {,v}movap{s,d} xmm/m128,xmm */ + /* vmovap{s,d} ymm/m256,ymm */ + case 0x29: /* {,v}movap{s,d} xmm,xmm/m128 */ + /* vmovap{s,d} ymm,ymm/m256 */ + fail_if(vex.pf...