Displaying 3 results from an estimated 3 matches for "vmovdqa32".
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vmovdqa
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
...48(%rdx,%r9), %rdx
.align 16, 0x90
.LBB0_1:
vmovd %r8d, %xmm0
vpbroadcastd %xmm0, %xmm0
vmovd %edi, %xmm1
vpbroadcastd %xmm1, %xmm1
vmovd %r10d, %xmm2
vpbroadcastd %xmm2, %xmm2
vmovd %esi, %xmm3
vpbroadcastd %xmm3, %xmm3
vmovdqa32 %xmm0, -48(%rdx)
vmovdqa32 %xmm1, -32(%rdx)
vmovdqa32 %xmm2, -16(%rdx)
vmovdqa32 %xmm3, (%rdx)
addq $1, %rax
addq $64, %rdx
cmpq %rcx, %rax
jl .LBB0_1
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.sec...
2017 Jun 21
2
AVX 512 Assembly Code Generation issues
...16
> movq %rsp, %rbp
> .Ltmp2:
> .cfi_def_cfa_register %rbp
> movq $-1024, %rax # imm = 0xFC00
> .p2align 4, 0x90
> .*LBB0_1: # %vector.body*
> * # =>This Inner Loop Header:
> Depth=1*
> * vmovdqa32 c+1024(%rax), %xmm0*
> * vmovdqa32 c+1040(%rax), %xmm1*
> * vpaddd b+1024(%rax), %xmm0, %xmm0*
> * vpaddd b+1040(%rax), %xmm1, %xmm1*
> * vmovdqa32 %xmm0, a+1024(%rax)*
> * vmovdqa32 %xmm1, a+1040(%rax)*
> * vmovdqa32 c+1056(%rax), %xmm0*
> * vmovdqa32 c+1072(%rax), %xmm1*
>...
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
...%r8d, %xmm0
> vpbroadcastd %xmm0, %xmm0
> vmovd %edi, %xmm1
> vpbroadcastd %xmm1, %xmm1
> vmovd %r10d, %xmm2
> vpbroadcastd %xmm2, %xmm2
> vmovd %esi, %xmm3
> vpbroadcastd %xmm3, %xmm3
> vmovdqa32 %xmm0, -48(%rdx)
> vmovdqa32 %xmm1, -32(%rdx)
> vmovdqa32 %xmm2, -16(%rdx)
> vmovdqa32 %xmm3, (%rdx)
> addq $1, %rax
> addq $64, %rdx
> cmpq %rcx, %rax
> jl .LBB0_1
> retq
> .Lfunc...