Displaying 4 results from an estimated 4 matches for "vmov_256b_rm".
2017 Jul 07
2
Unhandled reg/opcode register encoding VR2048 Error in backend
Hello,
I m working towards backend.
Here i need to define vector load and stores for 64 i32 elements. so in
x86instrinfo.td i wrote;
def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
"vmov_256B_rm\t{$src, $dst|$dst, $src}",
[(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],
IIC_MOV_MEM>, EVEX;
def VMOV_256B_MR : I<0x7F, M...
2017 Jul 08
5
Error in v64i32 type in x86 backend
...>>>>>>>>>>> written in x86instravx512. i need to define my vector instructions so i
>>>>>>>>>>>>>> wrote;
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst),
>>>>>>>>>>>>>> (ins i32mem:$src),
>>>>>>>>>>>>>> "vmov_256B_rm\t{$src, $dst|$dst, $src}",
>>>>>>>>>>>>>...
2017 Jul 08
2
Error in v64i32 type in x86 backend
Thank you. i understood how avx512 vector instructions are written in
x86instravx512. i need to define my vector instructions so i wrote;
def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
"vmov_256B_rm\t{$src, $dst|$dst, $src}",
[(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],
IIC_MOV_MEM>, EVEX;
def VMOV_256B_MR : I<0x7F, M...
2017 Jul 08
2
Error in v64i32 type in x86 backend
...t 8:41 PM hameeza ahmed <hahmed2305 at gmail.com>
>>> wrote:
>>>
>>>> Thank you. i understood how avx512 vector instructions are written in
>>>> x86instravx512. i need to define my vector instructions so i wrote;
>>>>
>>>> def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
>>>> i32mem:$src),
>>>> "vmov_256B_rm\t{$src, $dst|$dst, $src}",
>>>> [(set VR2048:$dst, (v64i32 (scalar_to_vector
>>>> (loadi32 addr:$src))))],
>>...