search for: vmmcall

Displaying 20 results from an estimated 45 matches for "vmmcall".

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2020 Feb 12
1
[PATCH 50/62] x86/sev-es: Handle VMMCALL Events
> On Feb 11, 2020, at 5:53 AM, Joerg Roedel <joro at 8bytes.org> wrote: > > ?From: Tom Lendacky <thomas.lendacky at amd.com> > > Implement a handler for #VC exceptions caused by VMMCALL instructions. > This patch is only a starting point, VMMCALL emulation under SEV-ES > needs further hypervisor-specific changes to provide additional state. > How about we just don?t do VMMCALL if we?re a SEV-ES guest? Otherwise we add thousands of cycles of extra latency for no good re...
2020 Feb 11
0
[PATCH 50/62] x86/sev-es: Handle VMMCALL Events
From: Tom Lendacky <thomas.lendacky at amd.com> Implement a handler for #VC exceptions caused by VMMCALL instructions. This patch is only a starting point, VMMCALL emulation under SEV-ES needs further hypervisor-specific changes to provide additional state. Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> [ jroedel at suse.de: Adapt to #VC handling infrastructure ] Co-developed-by: Joer...
2020 Apr 28
0
[PATCH v3 67/75] x86/vmware: Add VMware specific handling for VMMCALL under SEV-ES
From: Doug Covelli <dcovelli at vmware.com> This change adds VMware specific handling for #VC faults caused by VMMCALL instructions. Signed-off-by: Doug Covelli <dcovelli at vmware.com> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> [ jroedel at suse.de: - Adapt to different paravirt interface ] Co-developed-by: Joerg Roedel <jroedel at suse.de> Signed-off-by: Joerg Roedel <jroedel a...
2010 Jul 28
23
HVM hypercalls
Hi I need to use hypercalls from HVM domain (e.g. HYPERVISOR_add_to_physmap). However, it does not work when I am trying to invoke it from HVM Linux guest. Basically, I don''t see that anything happens on hypervisor''s side. I also grep''ed the guest code for ''vmmcall''/''vmcall'' and did not find anything. Is it possible to do it at all? Is it possible to make hypercalls from HVM domains or are they simply used for tools responsible to load HVM domain? Also, are they allowed (if allowed at all) from stubdom, ioemu, or both configurations...
2015 Nov 18
4
[PATCH 1/3] x86/xen: Avoid fast syscall path for Xen PV guests
...- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -216,6 +216,7 @@ > #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ > #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ > #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ > +#define X86_FEATURE_XENPV ( 8*32+16) /* Xen paravirtual guest */ > This bit is highly magical and I think we need Borislav's ack. --Andy
2015 Nov 18
4
[PATCH 1/3] x86/xen: Avoid fast syscall path for Xen PV guests
...- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -216,6 +216,7 @@ > #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ > #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ > #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ > +#define X86_FEATURE_XENPV ( 8*32+16) /* Xen paravirtual guest */ > This bit is highly magical and I think we need Borislav's ack. --Andy
2019 May 08
2
failed to build llvm since 25de7691a0e27c29c8d783a22373cc265571f5e9 on AMD platform
...good nopl nonstop_tsc cpuid extd_apicid amd_dcm aperfmperf pni pclmulqdq monitor ssse3 cx16 sse4_1 sse4_2 popcnt aes xsave avx lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 nodeid_msr topoext perfctr_core perfctr_nb cpb hw_pstate ssbd vmmcall arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold OS INFO on Debian 8: root at lkp-opteron1 /opt/rootfs/llvm_project/src/build# dpkg -l g++ cmake Desired=Unknown/Install/Remove/Purge/Hold | Status=Not/Inst/Conf-files/Unpacked/halF-conf/Half-in...
2019 May 09
3
failed to build llvm since 25de7691a0e27c29c8d783a22373cc265571f5e9 on AMD platform
...good nopl nonstop_tsc cpuid extd_apicid amd_dcm aperfmperf pni pclmulqdq monitor ssse3 cx16 sse4_1 sse4_2 popcnt aes xsave avx lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 nodeid_msr topoext perfctr_core perfctr_nb cpb hw_pstate ssbd vmmcall arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold > > > OS INFO on Debian 8: > root at lkp-opteron1 /opt/rootfs/llvm_project/src/build# dpkg -l g++ cmake > Desired=Unknown/Install/Remove/Purge/Hold > | Status=No...
2020 Apr 28
0
[PATCH v3 04/75] x86/cpufeatures: Add SEV-ES CPU feature
...lude/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -234,6 +234,7 @@ #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */ #define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */ #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */ +#define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RD...
2015 Nov 18
0
[PATCH 1/3] x86/xen: Avoid fast syscall path for Xen PV guests
...4f8010..0e4fe5b 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -216,6 +216,7 @@ #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ +#define X86_FEATURE_XENPV ( 8*32+16) /* Xen paravirtual guest */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 5774800..d315151 100644 --- a/ar...
2020 Apr 04
3
how to pick cipher for AES-NI enabled AMD GX-412TC SOC tincd at 100% CPU
...acc_power nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt topoext perfctr_nb bpext ptsc perfctr_llc cpb hw_pstate ssbd vmmcall bmi1 xsaveopt arat npt lbrv svm_lock nrip_save tsc_scale flushbyasid decodeassists pausefilter pfthreshold overflow_recov root at officelink01:~# openssl help Standard commands asn1parse ca ciphers cms crl crl2pkcs7 dgst dhparam...
2007 May 14
17
[ANNOUNCE] virtbench now has xen support
Hi all, I've been working on a set of easy-to-run benchmarks for hypervisor optimization called virtbench, and the latest commit adds Xen support. http://ozlabs.org/~rusty/virtbench http://ozlabs.org/~rusty/virtbench/?archive/tip.tar.bz2 >From the README: # Build the code make # Set the guest kernel location and maybe more vi ./SETTINGS # Run the benchmark (local mode)
2007 May 14
17
[ANNOUNCE] virtbench now has xen support
Hi all, I've been working on a set of easy-to-run benchmarks for hypervisor optimization called virtbench, and the latest commit adds Xen support. http://ozlabs.org/~rusty/virtbench http://ozlabs.org/~rusty/virtbench/?archive/tip.tar.bz2 >From the README: # Build the code make # Set the guest kernel location and maybe more vi ./SETTINGS # Run the benchmark (local mode)
2007 May 14
17
[ANNOUNCE] virtbench now has xen support
Hi all, I've been working on a set of easy-to-run benchmarks for hypervisor optimization called virtbench, and the latest commit adds Xen support. http://ozlabs.org/~rusty/virtbench http://ozlabs.org/~rusty/virtbench/?archive/tip.tar.bz2 >From the README: # Build the code make # Set the guest kernel location and maybe more vi ./SETTINGS # Run the benchmark (local mode)
2020 Feb 02
1
[OFF TOPIC] Teo En Ming's Guide to GPU/VGA Passthrough of NVidia GeForce GTX1650 to Windows 10 Virtual Machine using Linux KVM on Ubuntu 18.04.3 LTS Desktop Edition
...extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb hw_pstate sme ssbd sev ibpb vmmcall fsgsbase bmi1 avx2 smep bmi2 rdseed adx smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves clzero irperf xsaveerptr arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif overflow_recov succor smca flags...
2008 Oct 23
5
Why using hypercall_page ?
Hello, I am studing Xen hypercall now. I found that hypercall is invoked via hypercall_page, which is only filled with (in no-hypervisor-kernel-mode ): mov $i, %eax int $0x82 ret Why not invoked the hypercall directly by "int $0x82" ? What''s the advantage of using hypercall_page? Thanks, Wu _______________________________________________ Xen-devel mailing list
2006 Apr 06
20
[RFC] Hypercalls from HVM guests
Hi, I am currently working on hypercalls from HVM guests. I started with a set of Intel patches posted to xen-devel last September. I currently have code running for both 32-bit and 64-bit HVM guests running on a 64-bit hypervisor. I am curious why none of the original patches were accepted, and what I might need to do to make them acceptable. Is other work being done in this area that
2015 Nov 18
8
[PATCH 0/3] Fix and cleanup for 32-bit PV sysexit
The first patch fixes Xen PV regression introduced by 32-bit rewrite. Unlike the earlier version it uses ALTERNATIVE instruction and avoids using xen_sysexit (and sysret32 in compat mode) pv ops, as suggested by Andy. (I ended up patching TEST with XOR to avoid extra NOPs, even though I said yesterday it would be wrong. It's not wrong) As result of this patch irq_enable_sysexit and
2015 Nov 18
8
[PATCH 0/3] Fix and cleanup for 32-bit PV sysexit
The first patch fixes Xen PV regression introduced by 32-bit rewrite. Unlike the earlier version it uses ALTERNATIVE instruction and avoids using xen_sysexit (and sysret32 in compat mode) pv ops, as suggested by Andy. (I ended up patching TEST with XOR to avoid extra NOPs, even though I said yesterday it would be wrong. It's not wrong) As result of this patch irq_enable_sysexit and
2020 Apr 28
0
[PATCH v3 19/75] x86/boot/compressed/64: Add stage1 #VC handler
...eg) (GHCB_SEV_CPUID_REQ | \ + (((unsigned long)reg & 3) << 30) | \ + (((unsigned long)fn) << 32)) + +#define GHCB_SEV_CPUID_RESP 0x005UL +#define GHCB_SEV_TERMINATE 0x100UL + +#define GHCB_SEV_GHCB_RESP_CODE(v) ((v) & 0xfff) +#define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } + +void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code); + +static inline u64 lower_bits(u64 val, unsigned int bits) +{ + u64 mask = (1ULL << bits) - 1; + + return (val & mask); +} + +#endif diff --git a/arch/x86/include/asm/trap_defs.h b/arch/x86/include...