search for: vmlas

...on A series and the encoding will determine which will be used. In assembly files, the difference is mainly the type vs. the registers used. The problem we were trying to avoid a long time ago was well researched by Evan Cheng and it has shown that there is a pipeline stall between two sequential VMLAs (possibly due to the need of re-use of some registers) and this made code much slower than a sequence of VMLA+VMUL+VADD. Also, please note that, as accurate as cycle counts go, according to the A9 manual, one VFP VMLA takes almost as long as a pair of VMUL+VADD to provide the results, so a sequenc...

...will > determine which will be used. In assembly files, the difference is mainly > the type vs. the registers used. > > The problem we were trying to avoid a long time ago was well researched by > Evan Cheng and it has shown that there is a pipeline stall between two > sequential VMLAs (possibly due to the need of re-use of some registers) and > this made code much slower than a sequence of VMLA+VMUL+VADD. > > Also, please note that, as accurate as cycle counts go, according to the > A9 manual, one VFP VMLA takes almost as long as a pair of VMUL+VADD to > provide t...

Hi Tim, > > cortex-a15 vfpv4 : vmla instruction emitted (which is a NEON instruction) > > I get a VFP vmla here rather than a NEON one (clang -target > armv7-linux-gnueabihf -mcpu=cortex-a15): "vmla.f32 s0, s1, s2". Are > you seeing something different? > As per Renato comment above, vmla instruction is NEON instruction while vmfa is VFP instruction. Correct

Hi Sebastien, How many extra vmlas did you see in 433.milc due to disabling -vmlx-forwarding? As I mentioned earlier, I saw only two additional integer vmlx instructions when I tested. Could you send me your 433.milc compile setup? (os, flags, compiler version, etc.). I'd like to try to reproduce your results. Cheers, Lang....

On 12 February 2013 16:56, Sebastien DELDON-GNB <sebastien.deldon at st.com>wrote: > If this helps taking your decision, there are at least two benchmarks for > which disabling vmlx-forwarding makes a significant difference. > I think Evan's worry was to base this decision on visible and comprehensible benchmarks, such as the test-suite. If I get lucky I may be able to run

...is > used but test have made show significant improvements when disabled for > cortex-A9 (STEricsson Nova platform). > Hi Sebastien, The optimization does make sense for cortex-a9, I remember to have reviewed the patch myself and the A9 document clearly states the delays involved between VMLAs and that this was a solution. However, due to micro-architecture differences (as David explained), it may interfere with other non-Swift steps (or the lack of Swift steps) and produce worse code. It's not uncommon to see "is (isSwift())" around the code generation or optimization pas...

...erate call to a VLMA intrinsic I would have defined when it thinks it’s appropriate to generate one. > > No, and I'm not sure we should have one. > > I understand why you want one, but that's too much back-end knowledge to a front-end, and any pass that can transform a pair of VMLAs into an intrinsic call, can also transform into VMLA+VMUL+VADD. In this case, disabling the optimization is probably the best course of action. > > In your compiler, you may prefer to leave it always disabled, then you should set it when creating the Target. > > If we find that this o...

Understood, Same architecture, different micro-arch (implementation). Could this be the case that vmlx-forwarding make senses for SWIFT and not for ARM Cortex-A9 implementation ? It is enabled by default when -mcpu=cortex-a9 is used but test have made show significant improvements when disabled for cortex-A9 (STEricsson Nova platform). Best Regards Seb From: David Tweed [mailto:david.tweed at

...is small and that we decide to pay the price, but not until we know that the cost is. This was tested on real hardware. Time taken for a 4x4 matrix > multiplication: > What hardware? A7? A8? A9? A15? Also, as stated by Renato - "there is a pipeline stall between two > sequential VMLAs (possibly due to the need of re-use of some registers) and > this made code much slower than a sequence of VMLA+VMUL+VADD" , when i use > -mcpu=cortex-a15 as option, clang emits vmla instructions back to > back(sequential) . Is there something different with cortex-a15 regarding >...

...-end to generate call to a VLMA intrinsic I > would have defined when it thinks it’s appropriate to generate one. > No, and I'm not sure we should have one. I understand why you want one, but that's too much back-end knowledge to a front-end, and any pass that can transform a pair of VMLAs into an intrinsic call, can also transform into VMLA+VMUL+VADD. In this case, disabling the optimization is probably the best course of action. In your compiler, you may prefer to leave it always disabled, then you should set it when creating the Target. If we find that this optimization produces...

...t have made show significant improvements when disabled for cortex-A9 (STEricsson Nova platform). >> > > Hi Sebastien, > > The optimization does make sense for cortex-a9, I remember to have reviewed the patch myself and the A9 document clearly states the delays involved between VMLAs and that this was a solution. > > However, due to micro-architecture differences (as David explained), it may interfere with other non-Swift steps (or the lack of Swift steps) and produce worse code. It's not uncommon to see "is (isSwift())" around the code generation or optim...

Hi Renato, Indeed problem is with generation of vmla.f64. Affected benchmark is MILC from SPEC 2006 suite and disabling vmlx forwarding gives a 10% speed-up on complete benchmark execution ! So it is worth a try. Now going back to vmla generation through LLMV intrinsic usage. I've looked at .td file and it seems to me that when there is a "pattern" to generate instruction, no

...VLMA intrinsic I >> would have defined when it thinks it’s appropriate to generate one. >> > No, and I'm not sure we should have one. > > I understand why you want one, but that's too much back-end knowledge to a > front-end, and any pass that can transform a pair of VMLAs into an > intrinsic call, can also transform into VMLA+VMUL+VADD. In this case, > disabling the optimization is probably the best course of action. > > In your compiler, you may prefer to leave it always disabled, then you > should set it when creating the Target. > > If we fin...

...fine on A15 without any crash, i went ahead with cortex-a8 option. I don't think i will get A8 hardware soon, can someone please check it on A8 hardware as well (Sorry for the trouble)? > > > Also, as stated by Renato - "there is a pipeline stall between two >> sequential VMLAs (possibly due to the need of re-use of some registers) and >> this made code much slower than a sequence of VMLA+VMUL+VADD" , when i use >> -mcpu=cortex-a15 as option, clang emits vmla instructions back to >> back(sequential) . Is there something different with cortex-a15 reg...

...mcpu=cortex-a9 is used but test have made show significant improvements when disabled for cortex-A9 (STEricsson Nova platform). Hi Sebastien, The optimization does make sense for cortex-a9, I remember to have reviewed the patch myself and the A9 document clearly states the delays involved between VMLAs and that this was a solution. However, due to micro-architecture differences (as David explained), it may interfere with other non-Swift steps (or the lack of Swift steps) and produce worse code. It's not uncommon to see "is (isSwift())" around the code generation or optimization pas...

...front-end to generate call to a VLMA intrinsic I would have defined when it thinks it's appropriate to generate one. No, and I'm not sure we should have one. I understand why you want one, but that's too much back-end knowledge to a front-end, and any pass that can transform a pair of VMLAs into an intrinsic call, can also transform into VMLA+VMUL+VADD. In this case, disabling the optimization is probably the best course of action. In your compiler, you may prefer to leave it always disabled, then you should set it when creating the Target. If we find that this optimization produces...

...st Regards Seb From: Lang Hames [mailto:lhames at gmail.com] Sent: Wednesday, February 13, 2013 8:31 AM To: Renato Golin Cc: Sebastien DELDON-GNB; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] RE : Is there any llvm neon intrinsic that maps to vmla.f32 instruction ? Hi Sebastien, How many extra vmlas did you see in 433.milc due to disabling -vmlx-forwarding? As I mentioned earlier, I saw only two additional integer vmlx instructions when I tested. Could you send me your 433.milc compile setup? (os, flags, compiler version, etc.). I'd like to try to reproduce your results. Cheers, Lang. O...