search for: vmexit

...est VMs where I wish to run guest VMs in a loop. I wish to use a core to schedule a guest VM, service it eg. execute an ISR etc and then return to the context of Xen on that core, so that I can then schedule the next VM on that core. In doing all this, the goal is to avoid the calls to VMEntry and VMExit. Is there a workaround for this to be done or will I always have to face a VMExit to return to the Xen context on that core ? Looking forward to some pointers. Thanks, Devdutt. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xens...

Cleanup vmx vmexit handler. Current code doesn''t handle vmexits caused by triple fault, INIT, SIPI, etc, which are listed in IA32 Architecture System Programming Guide 2, Appendix I VMX Basic Exit Reasons, and calls __hvm_bug() when not handling such cases, actually domain crash should be good enough. Also v...

Hi, Lately I was puzzled by a vmexit reason 31 which was defined as EXIT_REASON_MSR_READ I allocated an array in xen data section and assigned its MFN to an EPT entry of a domainU, I thought the domU could access this array but after that the domainU crashed and xen gave me this exit reason "Bad vmexit (reason 31)" But ther...

yujiageng734 wrote: > Hi, > > I am trying to use your gdbsx. But I don''t know how to make a 32bit > dom0 running on 64bit hypervisor. Can you explain this for me? I''m > extremely grateful to you. Hmm.. good question. I don''t know, it''s always done for me here. One option would be to just download OVM from edelivery.oracle.com,

This patch enables tracing VMEXIT/ENTRY for 64-bit systems (are there any 32-bit VT enabled systems out there?) Signed-off by Himanshu Raj (rhim.list@nosuchaddr.com) -- ------------------------------------------------------------------------- Himanshu Raj PhD Student, GaTech (www.cc.gatech.edu/~rhim) I prefer to receive attachme...

Is there any particular reason why on 32-bits the order is VMLOAD then HVM_SAVE_ALL_NOSEGREGS, while on 64-bits its is the other way around? Trying to put in the saving of EAX, I could save a GET_CURRENT() on 32-bits if I could order things the same way as on 64-bits. Also, both versions seem to have a redundant GET_CURRENT() right after the clgi/sti sequence - again, is there a particular reason

Remove the do_nmi() call from the vmexit logic, as the NMI is held pending and will be handled in the context of the host when the STGI instruction is executed. This patch only modifies AMD-V code. This patch is required even without the other Xenoprofile patches applied. Applies cleanly to c/s 11831. Please apply to xen-unstable.hg r...

...use of the dedicated guest VMCS field. This is being fixed with this patch. What is puzzling me to a certain degree is that while there is a guest VMCS field for this MSR, there''s no equivalent host load field, but there''s also no indication that the MSR would be cleared during a vmexit. Can someone at Intel perhaps give a statement on this? I would really be possible to avoid the intercept on DebugCtl reads altogether, but that would require new support functions to individually disable read and write intercepts (which currently are always handled as a pair). I''m not su...

Attached. -Himanshu -- ------------------------------------------------------------------------- Himanshu Raj PhD Student, GaTech (www.cc.gatech.edu/~rhim) I prefer to receive attachments in an open, non-proprietary format. ------------------------------------------------------------------------- _______________________________________________ Xen-devel mailing list

Hi, Keir, This patch is to fix the problem of Linux guest installation failure and Windows 2000 boot failure.       In the early code, we use vmx_vmexit_handler() -> vmx_io_instruction() function to emulate I/O instructions. But now, we use vmx_vmexit_handler() -> handle_mmio -> hvm_emulate_one() -> x86_emulate() to emulate I/O instructions. Also nowadays, the realmode emulation code walks through the path: vmx_realmode() -> realmode...

The self_nmi() code cause''s an NMI to be triggered by sending an APIC message to the local processor. However, NMIs are blocked by the VMEXIT, until the next iret or VMENTER. Volume 3 Chapter 27 Section 1 of the Intel SDM states: An NMI causes subsequent NMIs to be blocked, but only after the VM exit completes. As a result, as soon as the VMENTER happens, an immediate VMEXIT happens as a result of the queued NMI. We have seen hundred...

Hi I am working on a project using WINDOWS guest on XEN archticture. I have a couple of questions. As I understand when a VM exit occurs due to I/O like say a mouse interrupt -- the XEN hypervisor gets a notification and it forwards the I/O request to the qemu-dm in Domain-0 via an event channel. Now during this VM exit , is the guest OS blocked ? Specifically, what about VGA writes are they

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR perf/x86: add a function to get the lbr stack KVM/vmx: enable lbr for the guest arch/x86/events/intel/lbr.c...

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR perf/x86: add a function to get the lbr stack KVM/vmx: enable lbr for the guest arch/x86/events/intel/lbr.c...

hello list: I add some code to xen-3.1.0-src\xen\arch\x86\hvm\vmx\vmx.c to export some information when vmx_vmexit_handler() executed: ------------------------------------------------------------------------------------------------- --- vmx.c 2007-05-18 22:45:22.000000000 +0800 +++ vmx-patch.c 2008-11-24 14:19:18.000000000 +0800 @@ -50,7 +50,9 @@ #include <asm/hvm/vpt.h> #include <public/hvm/save.h&...

> + > +/* The exitcode is in native SVM/VMX format. The forced exitcode > + * is in generic format. > + */ Introducing a 3rd format of exitcode is over-complicated IMO. > +enum nestedhvm_vmexits > +nestedhvm_vcpu_vmexit(struct vcpu *v, struct cpu_user_regs *regs, > + uint64_t exitcode) > +{ I doubt about the necessary of this kind of wrapper. In single layer virtualization, SVM and VMX have its own handler for each VM exit. Only when certain common function is invoked, the c...

...om wasting whole timeslice Retry threshold is the easiest solution, regardless of its ugliness [4]. Another minor design flaw is that formerly first VCPU gets appended to the tail when it decides to queue; is the performance gain worth it? Thanks. --- 1: Pause Loop Exiting is almost certain to vmexit in that case: we default to 4096 TSC cycles on KVM, and pending loop is longer than 4 (4096/PSPIN_THRESHOLD). We would also vmexit if critical section was longer than 4k. 2: In this example, vpus 1 and 2 use the lock while 3 never gets there. VCPU: 1 2 3 lock()...

...om wasting whole timeslice Retry threshold is the easiest solution, regardless of its ugliness [4]. Another minor design flaw is that formerly first VCPU gets appended to the tail when it decides to queue; is the performance gain worth it? Thanks. --- 1: Pause Loop Exiting is almost certain to vmexit in that case: we default to 4096 TSC cycles on KVM, and pending loop is longer than 4 (4096/PSPIN_THRESHOLD). We would also vmexit if critical section was longer than 4k. 2: In this example, vpus 1 and 2 use the lock while 3 never gets there. VCPU: 1 2 3 lock()...

> From: Thomas Gleixner [mailto:tglx at linutronix.de] > Sent: Saturday, February 11, 2017 02:02 > ... > That's important if the stuff happens cross CPU. If the update happens on > the same CPU then this is a different story and as there are VMexits > involved they might provide the required ordering already. But I can't tell > as I have no idea how that host side thing is done. > > tglx IMO Hyper-V TSC page clocksource here seems pretty similar to KVM's pvclock, So I would guess "the structure is only updated just...

> From: Thomas Gleixner [mailto:tglx at linutronix.de] > Sent: Saturday, February 11, 2017 02:02 > ... > That's important if the stuff happens cross CPU. If the update happens on > the same CPU then this is a different story and as there are VMexits > involved they might provide the required ordering already. But I can't tell > as I have no idea how that host side thing is done. > > tglx IMO Hyper-V TSC page clocksource here seems pretty similar to KVM's pvclock, So I would guess "the structure is only updated just...