Displaying 20 results from an estimated 56 matches for "vmentry".
2013 Oct 30
3
[PATCH 4/4] XSA-60 security hole: flush cache when vmentry back to UC guest
From 159251a04afcdcd8ca08e9f2bdfae279b2aa5471 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Thu, 31 Oct 2013 06:38:15 +0800
Subject: [PATCH 4/4] XSA-60 security hole: flush cache when vmentry back to UC guest
This patch flush cache when vmentry back to UC guest, to prevent
cache polluted by hypervisor access guest memory during UC mode.
The elegant way to do this is, simply add wbinvd just before vmentry.
However, currently wbinvd before vmentry will mysteriously trigger
lapic timer i...
2013 Nov 25
14
[PATCH] VMX: wbinvd when vmentry under UC
From e2d47e2f75bac6876b7c2eaecfe946966bf27516 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Tue, 26 Nov 2013 04:53:17 +0800
Subject: [PATCH] VMX: wbinvd when vmentry under UC
This patch flush cache when vmentry back to UC guest, to prevent
cache polluted by hypervisor access guest memory during UC mode.
However, wbinvd is a _very_ time consuming operation, so
1. wbinvd ... timer has a good possibility to expire while
irq disabled, it then would be delayed...
2007 Oct 29
4
Avoiding VmEntry/VmExit.
...rvices to guest VMs where I wish to run guest VMs
in a loop.
I wish to use a core to schedule a guest VM, service it eg. execute an ISR
etc and then return to the context of Xen on that core, so that I can then
schedule the next VM on that core.
In doing all this, the goal is to avoid the calls to VMEntry and VMExit. Is
there a workaround for this to be done or will I always have to face a
VMExit to return to the Xen context on that core ?
Looking forward to some pointers.
Thanks,
Devdutt.
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Xen-devel@lists.xensource.com
http:/...
2006 Apr 13
0
minor patch for tracing VMEXIT/VMENTRY for 64 bit system
Attached.
-Himanshu
--
-------------------------------------------------------------------------
Himanshu Raj
PhD Student, GaTech (www.cc.gatech.edu/~rhim)
I prefer to receive attachments in an open, non-proprietary format.
-------------------------------------------------------------------------
_______________________________________________
Xen-devel mailing list
2006 Apr 14
1
[PATCH][VT] minor patch for tracing VMEXIT/VMENTRY for 64 bit systems
This patch enables tracing VMEXIT/ENTRY for 64-bit systems (are there any 32-bit
VT enabled systems out there?)
Signed-off by Himanshu Raj (rhim.list@nosuchaddr.com)
--
-------------------------------------------------------------------------
Himanshu Raj
PhD Student, GaTech (www.cc.gatech.edu/~rhim)
I prefer to receive attachments in an open, non-proprietary format.
2010 Aug 18
4
RE: [PATCH 05/15] Nested Virtualization: core
...> +
> + /* Prepare for running the guest. Do some final SVM/VMX
> + * specific tweaks if necessary to make it work.
> + */
> + rc = hvm_nestedhvm_vcpu_vmexit(v, regs, exitcode);
> + hvm->nh_hostflags.fields.forcevmexit = 0;
> + if (rc) {
> + hvm->nh_hostflags.fields.vmentry = 0;
> + return NESTEDHVM_VMEXIT_FATALERROR;
> + }
Thx, Eddie
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2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
This patch series enables the Last Branch Recording feature for the
guest. Instead of trapping each LBR stack MSR access, the MSRs are
passthroughed to the guest. Those MSRs are switched (i.e. load and
saved) on VMExit and VMEntry.
Test:
Try "perf record -b ./test_program" on guest.
Wei Wang (4):
KVM/vmx: re-write the msr auto switch feature
KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR
perf/x86: add a function to get the lbr stack
KVM/vmx: enable lbr for the guest
arch/x86/events/intel/lbr.c | 23 ++...
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
This patch series enables the Last Branch Recording feature for the
guest. Instead of trapping each LBR stack MSR access, the MSRs are
passthroughed to the guest. Those MSRs are switched (i.e. load and
saved) on VMExit and VMEntry.
Test:
Try "perf record -b ./test_program" on guest.
Wei Wang (4):
KVM/vmx: re-write the msr auto switch feature
KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR
perf/x86: add a function to get the lbr stack
KVM/vmx: enable lbr for the guest
arch/x86/events/intel/lbr.c | 23 ++...
2008 Mar 14
4
[PATCH] vmx: fix debugctl handling
I recently realized that the original way of dealing with the DebugCtl
MSR on VMX failed to make use of the dedicated guest VMCS field. This
is being fixed with this patch.
What is puzzling me to a certain degree is that while there is a guest
VMCS field for this MSR, there''s no equivalent host load field, but
there''s also no indication that the MSR would be cleared during a
2013 Apr 09
39
[PATCH 0/4] Add posted interrupt supporting
From: Yang Zhang <yang.z.zhang@Intel.com>
The follwoing patches are adding the Posted Interrupt supporting to Xen:
Posted Interrupt allows vAPIC interrupts to inject into guest directly
without any vmexit.
- When delivering a interrupt to guest, if target vcpu is running,
update Posted-interrupt requests bitmap and send a notification event
to the vcpu. Then the vcpu will handle this
2009 Feb 10
7
hang on restore in 3.3.1
...200130258168716 (+ 205) switch_infnext [ new_domid =
0x00000062, time = 786, r_time = 30000000 ]
CPU0 200130258169338 (+ 622) __enter_scheduler [
prev<domid:edomid> = 0x00000000 : 0x00000000, next<domid:edomid> =
0x00000062 : 0x00000000 ]
CPU0 200130258175532 (+ 6194) VMENTRY [ dom:vcpu = 0x00000062 ]
CPU0 200130258179633 (+ 4101) VMEXIT [ dom:vcpu = 0x00000062,
exitcode = 0x0000004e, rIP = 0x0000000080a562b9 ]
CPU0 0 (+ 0) MMIO_AST_WR [ address = 0xfee000b0, data =
0x00000000 ]
CPU0 0 (+ 0) PF_XEN [ dom:vcpu = 0x00000062, errorcode =...
2017 Sep 25
2
[PATCH v1 1/4] KVM/vmx: re-write the msr auto switch feature
...t; +static void update_msr_autoload_count_max(void)
> +{
> + u64 vmx_msr;
> + int n;
> +
> + /*
> + * According to the Intel SDM, if Bits 27:25 of MSR_IA32_VMX_MISC is
> + * n, then (n + 1) * 512 is the recommended max number of MSRs to be
> + * included in the VMExit and VMEntry MSR auto switch list.
> + */
> + rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
> + n = ((vmx_msr & 0xe000000) >> 25) + 1;
> + msr_autoload_count_max = n * KVM_VMX_DEFAULT_MSR_AUTO_LOAD_COUNT;
> +}
> +
Any reasons to do this if it's unlikely that we'll ever update more t...
2017 Sep 25
2
[PATCH v1 1/4] KVM/vmx: re-write the msr auto switch feature
...t; +static void update_msr_autoload_count_max(void)
> +{
> + u64 vmx_msr;
> + int n;
> +
> + /*
> + * According to the Intel SDM, if Bits 27:25 of MSR_IA32_VMX_MISC is
> + * n, then (n + 1) * 512 is the recommended max number of MSRs to be
> + * included in the VMExit and VMEntry MSR auto switch list.
> + */
> + rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
> + n = ((vmx_msr & 0xe000000) >> 25) + 1;
> + msr_autoload_count_max = n * KVM_VMX_DEFAULT_MSR_AUTO_LOAD_COUNT;
> +}
> +
Any reasons to do this if it's unlikely that we'll ever update more t...
2014 May 12
3
[PATCH v10 03/19] qspinlock: Add pending bit
...xample, vpus 1 and 2 use the lock while 3 never gets there.
VCPU: 1 2 3
lock() // we are the holder
pend() // we have pending bit
vmexit // while in PSPIN_THRESHOLD loop
unlock()
vmentry
SPINNING // for {;;} loop
vmexit
vmentry
lock()
pend()
vmexit
unlock()
vmentry
SPINNING
vmexit
vmentry
--- loop ---...
2014 May 12
3
[PATCH v10 03/19] qspinlock: Add pending bit
...xample, vpus 1 and 2 use the lock while 3 never gets there.
VCPU: 1 2 3
lock() // we are the holder
pend() // we have pending bit
vmexit // while in PSPIN_THRESHOLD loop
unlock()
vmentry
SPINNING // for {;;} loop
vmexit
vmentry
lock()
pend()
vmexit
unlock()
vmentry
SPINNING
vmexit
vmentry
--- loop ---...
2017 Sep 25
0
[PATCH v1 1/4] KVM/vmx: re-write the msr auto switch feature
This patch clarifies a vague statement in the SDM: the recommended maximum
number of MSRs that can be automically switched by CPU during VMExit and
VMEntry is 512, rather than 512 Bytes of MSRs.
Depending on the CPU implementations, it may also support more than 512
MSRs to be auto switched. This can be calculated by
(MSR_IA32_VMX_MISC[27:25] + 1) * 512.
Signed-off-by: Wei Wang <wei.w.wang at intel.com>
---
arch/x86/kvm/vmx.c | 72 +++++++++++...
2007 Feb 26
4
[PATCH][xentrace][HVM] introduce HVM tracing to unify SVM and VMX tracing
Hello,
this patch introduces HVM tracing: one tracing class for both, SVM and
VMX.
It adds several new trace events. So we can differentiate between them
in the xentrace formats file and format each event''s data items
appropriately. With this patch the xentrace_format output is much more
informative.
The previous simple tracing in SVM and VMX is completely replaced.
Unfortunately I
2017 Sep 25
1
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
On 25/09/2017 06:44, Wei Wang wrote:
> Passthrough the LBR stack to the guest, and auto switch the stack MSRs
> upon VMEntry and VMExit.
>
> Signed-off-by: Wei Wang <wei.w.wang at intel.com>
This has to be enabled separately for each guest, because it may prevent
live migration to hosts with a different family/model.
Paolo
> ---
> arch/x86/kvm/vmx.c | 50 ++++++++++++++++++++++++++++++++++++++++++++...
2017 Sep 25
1
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
On 25/09/2017 06:44, Wei Wang wrote:
> Passthrough the LBR stack to the guest, and auto switch the stack MSRs
> upon VMEntry and VMExit.
>
> Signed-off-by: Wei Wang <wei.w.wang at intel.com>
This has to be enabled separately for each guest, because it may prevent
live migration to hosts with a different family/model.
Paolo
> ---
> arch/x86/kvm/vmx.c | 50 ++++++++++++++++++++++++++++++++++++++++++++...
2020 Sep 14
0
Re: [ovirt-users] Re: Testing ovirt 4.4.1 Nested KVM on Skylake-client (core i5) does not work
...ure policy="require" name="pdpe1gb"/>
> > <feature policy="require" name="ibpb"/>
> > <feature policy="require" name="amd-ssbd"/>
> > <feature policy="require" name="skip-l1dfl-vmentry"/>
> > <feature policy="require" name="mpx"/>
> > </cpu
>
> Thanks for the report!
>
> Would you like to open a bug about this?
>
> A possible fix is probably to pass relevant options to the
> virt-install command in ovirt-...