search for: vmenter

The self_nmi() code cause''s an NMI to be triggered by sending an APIC message to the local processor. However, NMIs are blocked by the VMEXIT, until the next iret or VMENTER. Volume 3 Chapter 27 Section 1 of the Intel SDM states: An NMI causes subsequent NMIs to be blocked, but only after the VM exit completes. As a result, as soon as the VMENTER happens, an immediate VMEXIT happens as a result of the queued NMI. We have seen hundreds of iterations of this VMEXIT/V...

This patch implements a new mechanism to buffer the MMIO_WRITE and PIO_WRITE packet in a queue, and then submit them to qemu-dm in batch. This could save a lot of domain switch time. We implement this as a generic one to do ioreq in batch. However, we only use it to batch the MMIO_WIRTE request for stdvga(0xA0000-0xC0000) in order to solve the win2k boot issue for hvm domain. Without this patch,

Hello, this patch introduces HVM tracing: one tracing class for both, SVM and VMX. It adds several new trace events. So we can differentiate between them in the xentrace formats file and format each event''s data items appropriately. With this patch the xentrace_format output is much more informative. The previous simple tracing in SVM and VMX is completely replaced. Unfortunately I

> On 12/08/2016 08:45 PM, Li, Liang Z wrote: > > What's the conclusion of your discussion? It seems you want some > > statistic before deciding whether to ripping the bitmap from the ABI, > > am I right? > > I think Andrea and David feel pretty strongly that we should remove the > bitmap, unless we have some data to support keeping it. I don't feel as >

> On 12/08/2016 08:45 PM, Li, Liang Z wrote: > > What's the conclusion of your discussion? It seems you want some > > statistic before deciding whether to ripping the bitmap from the ABI, > > am I right? > > I think Andrea and David feel pretty strongly that we should remove the > bitmap, unless we have some data to support keeping it. I don't feel as >

Hi guys, At a loss trying to figure why if (has_eflag(X86_EFLAGS_ID)) returns false in my HVM domU. Standard function has_eflag() in cpucheck.c running in real mode. Works fine on PV dom0, but fails when guest is booting on my hybrid dom0. LMK if any ideas. I''ll keep digging in the manuals, but nothing so far. thanks, Mukesh

Attached is patch for HVM guests (VMX only) that prints VMCS areas for all vcpus. A new hotkey (''v'') triggers the dump. We also print VMCS for current processor when vmenter fails. -boris _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...o. Changing topic but still about the ABI features needed, so it may be relevant for this discussion: 1) vNUMA locality: i.e. allowing host to specify which vNODEs to take memory from, using alloc_pages_node in guest. So you can ask to take X pages from vnode A, Y pages from vnode B, in one vmenter. 2) allowing qemu to tell the guest to stop inflating the balloon and report a fragmentation limit being hit, when sync compaction powered allocations fails at certain power-of-two order granularity passed by qemu to the guest. This order constraint will be passed by default for hugetl...

Am 29.08.2018 um 23:46 schrieb Stephen John Smoogen <smooge at gmail.com>: > > On Wed, 29 Aug 2018 at 17:41, Leon Fauster via CentOS <centos at centos.org> wrote: >> Since the update from kernel-2.6.32-754.2.1.el6.x86_64 >> to kernel-2.6.32-754.3.5.el6.x86_64 I can not boot my >> KVM guests anymore!? The workstation panics immediately! >> >> I

Hello, I''ve had a look at PVH support, and I have a few questions: - events are still dispatched the PV way through the callback, right? - I guess FPU errors don''t trigger an INT13, so I don''t need to handle that? - How about the console and store MFNs from the boot info? Are they still MFNs, or actually PFNs? - How about PV network in non-copy mode? It used to be

Hi, I have noticed that, in the code of linux/drivers/xen/balloon.c, there exists the snippet as this: static int __init balloon_init(void) { unsigned long pfn; struct page *page; if (!xen_pv_domain()) return -ENODEV; ..... } Does it means the driver will not work in HVM? If so, where is the HVN-enabled code for that? 2010-11-16 Rui Chu _______________________________________________

Hello, I read in the announce of Xen 3.2.0 released that it has "preliminary support for a wider range of bootloaders in fully virtualised (HVM) guests, using full emulation of x86 ''real mode''" . I''d like to know what is the level of the emulation of x86 ''real mode''? I ask that because I tried to install OpenSuse 10.3 (I used the iso file

This patch series tidies up a few bits ofthe nested p2m code. The main thing it does is reorganize the locking so that most of the changes to nested p2m tables happen only under the p2m lock, and the nestedp2m lock is only needed to reassign p2m tables to new cr3 values. Changes since v1: - a few minor fixes - more sensible flushing policy in p2m_get_nestedp2m() - smoke-tested this time!

This patch series is based on the VM introspection patches (https://lore.kernel.org/kvm/20200721210922.7646-1-alazar at bitdefender.com/), extending the introspection API with EPT Views and Virtualization Exceptions (#VE) support. The purpose of this series is to get an initial feedback and to see if we are on the right track, especially because the changes made to add the EPT views are not small

...d writes rather than using the out-of-sync mechanism. The out-of-sync mechanism requires three page faults, two of which entail relative expensive shadow operations: marking a page out of sync, and bringing it back into sync. In the case of HVM guests, the faults also cause three expensive vmexit/vmenter cycles. Our emulated writes requires only two page faults, and each fault is less expensive. Also, the overhead of many individual shadow operations is less in the newer code than in the old code. We have a number of potential optimizations in mind for the near future: * Removing writable mappi...

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

This issue I am encountering seems to only happen on multi-socket machines. It also does not help that the only multi-socket box I have is an Romley-EP (so two socket SandyBridge CPUs). The other SandyBridge boxes I''ve (one socket) are not showing this. Granted they are also a different model (42). The problem is that when I run ''perf top'' within an SMP PVHVM guest,