Displaying 9 results from an estimated 9 matches for "vmaskmovp".
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vmaskmovps
2016 Jan 23
2
how to force llvm generate gather intrinsic
...answers. My immediate motivation is to improve the masked load/store ops for an AVX target. If we can fix scatter/gather similarly, that would be great.
Can we legalize the same set of masked load/store operations for AVX1 as AVX2? If I'm understanding them correctly, the AVX1 FP instructions (vmaskmovps/pd) can be used in place of the AVX2 int instructions (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we do this for other missing integer ops for an AVX1 target either in x86 lowering or in the tablegen patterns.
Elena - I'm not too familiar with the vectorizers or sca...
2016 Feb 25
2
how to force llvm generate gather intrinsic
...answers. My immediate motivation is to improve the masked load/store ops for an AVX target. If we can fix scatter/gather similarly, that would be great.
Can we legalize the same set of masked load/store operations for AVX1 as AVX2? If I'm understanding them correctly, the AVX1 FP instructions (vmaskmovps/pd) can be used in place of the AVX2 int instructions (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we do this for other missing integer ops for an AVX1 target either in x86 lowering or in the tablegen patterns.
Elena - I'm not too familiar with the vectorizers or sca...
2016 Feb 24
0
how to force llvm generate gather intrinsic
...ion is to improve the
> masked load/store ops for an AVX target. If we can fix scatter/gather
> similarly, that would be great.
>
> Can we legalize the same set of masked load/store operations for AVX1 as
> AVX2? If I'm understanding them correctly, the AVX1 FP instructions
> (vmaskmovps/pd) can be used in place of the AVX2 int instructions
> (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we
> do this for other missing integer ops for an AVX1 target either in x86
> lowering or in the tablegen patterns.
>
> Elena - I'm not too familiar wi...
2016 Feb 25
0
how to force llvm generate gather intrinsic
...ion is to improve the
> masked load/store ops for an AVX target. If we can fix scatter/gather
> similarly, that would be great.
>
> Can we legalize the same set of masked load/store operations for AVX1 as
> AVX2? If I'm understanding them correctly, the AVX1 FP instructions
> (vmaskmovps/pd) can be used in place of the AVX2 int instructions
> (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we
> do this for other missing integer ops for an AVX1 target either in x86
> lowering or in the tablegen patterns.
>
> Elena - I'm not too familiar wi...
2016 Feb 25
2
how to force llvm generate gather intrinsic
...t; the masked load/store ops for an AVX target. If we can fix scatter/gather
>> similarly, that would be great.
>>
>> Can we legalize the same set of masked load/store operations for AVX1 as
>> AVX2? If I'm understanding them correctly, the AVX1 FP instructions
>> (vmaskmovps/pd) can be used in place of the AVX2 int instructions
>> (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we
>> do this for other missing integer ops for an AVX1 target either in x86
>> lowering or in the tablegen patterns.
>>
>> Elena - I'm...
2016 Jan 23
2
how to force llvm generate gather intrinsic
Thanks Sanjay for highlighting this, few days back I also faced similar problem
while generating masked store in avx1 mode, found its only supported under
avx2 else we scalarize it.
> 1) I did not switch-on masked_load/store to AVX1, I can do this.
Yes Elena, This should be supported for FP type in avx1 mode (for INT type, I doubt X86 has masked_load/store instruction in avx1 mode).
2016 Feb 26
2
how to force llvm generate gather intrinsic
...ion is to improve the
> masked load/store ops for an AVX target. If we can fix scatter/gather
> similarly, that would be great.
>
> Can we legalize the same set of masked load/store operations for AVX1 as
> AVX2? If I'm understanding them correctly, the AVX1 FP instructions
> (vmaskmovps/pd) can be used in place of the AVX2 int instructions
> (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we
> do this for other missing integer ops for an AVX1 target either in x86
> lowering or in the tablegen patterns.
>
> Elena - I'm not too familiar wi...
2016 Feb 26
0
how to force llvm generate gather intrinsic
...answers. My immediate motivation is to improve the masked load/store ops for an AVX target. If we can fix scatter/gather similarly, that would be great.
Can we legalize the same set of masked load/store operations for AVX1 as AVX2? If I'm understanding them correctly, the AVX1 FP instructions (vmaskmovps/pd) can be used in place of the AVX2 int instructions (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we do this for other missing integer ops for an AVX1 target either in x86 lowering or in the tablegen patterns.
Elena - I'm not too familiar with the vectorizers or sca...
2016 Feb 26
0
how to force llvm generate gather intrinsic
...t; the masked load/store ops for an AVX target. If we can fix scatter/gather
>> similarly, that would be great.
>>
>> Can we legalize the same set of masked load/store operations for AVX1 as
>> AVX2? If I'm understanding them correctly, the AVX1 FP instructions
>> (vmaskmovps/pd) can be used in place of the AVX2 int instructions
>> (vpmaskmovd/q), just with domain crossing penalties thrown in. I think we
>> do this for other missing integer ops for an AVX1 target either in x86
>> lowering or in the tablegen patterns.
>>
>> Elena - I'm...